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description the 7560 group is the 8-bit microcomputer based on the 740 fam- ily core technology. the 7560 group has the lcd drive control circuit, an 8-channel a- d/d-a converter, uart and pwm as additional functions. the various microcomputers in the 7560 group include variations of internal memory size and packaging. for details, refer to the section on part numbering. for details on availability of microcomputers in the 7560 group, refer the section on group expansion. features basic machine-language instructions ....................................... 71 the minimum instruction execution time ............................ 0.5 s (at 8 mhz oscillation frequency) memory size rom ................................................................ 32 k to 60 k bytes ram ............................................................... 1024 to 2560 bytes programmable input/output ports ............................................. 55 software pull-up resistors .................................................... built-in output ports ................................................................................. 8 input ports .................................................................................... 1 interrupts .................................................. 17 sources, 16 vectors (includes key input interrupt) timers ........................................................... 8-bit ? 3, 16-bit ? 2 serial i/o1 ..................... 8-bit ? 1 (uart or clock-synchronous) serial i/o2 .................................... 8-bit ? 1 (clock-synchronous) pwm output .................................................................... 8-bit ? 1 a-d converter .................................................. 8-bit ? 8 channels d-a converter .................................................. 8-bit ? 2 channels lcd drive control circuit bias ................................................................................... 1/2, 1/3 duty ............................................................................ 1/2, 1/3, 1/4 common output .......................................................................... 4 segment output ......................................................................... 40 2 clock generating circuits (connect to external ceramic resonator or quartz-crystal oscillator) watchdog timer ............................................................. 14-bit ? 1 power source voltage ................................................ 2.2 to 5.5 v power dissipation in high-speed mode ........................................................... 40 mw (at 8 mhz oscillation frequency, at 5 v power source voltage) in low-speed mode .............................................................. 60 w (at 32 khz oscillation frequency, at 3 v power source voltage) operating temperature range ................................... 20 to 85? applications camera, household appliances, consumer electronics, etc. 7560 group mitsubishi microcomputers single-chip 8-bit cmos microcomputer package type : 100p6s-a fig. 1 pin configuration of m37560mf-xxxfp pin configuration (top view) 1 23 45 67891 01 11 21 314151617181 9202 122232425262 72 82 93 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 46 4 7 4 8 4 9 5 0 51 52 5 3 5 4 5 5 5 6 5 7 58 5 9 6 0 6 1 62 63 6 4 6 5 6 6 6 7 6 8 6 9 7 0 71 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 9 0 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 9 10 0 m37560mf-xxxfp s e g 9 p 3 1 / s e g 1 9 p 3 0 / s e g 1 8 p 3 2 / s e g 2 0 p 3 3 / s e g 2 1 p 3 4 / s e g 2 2 s e g 1 0 s e g 1 1 s e g 1 2 s e g 1 3 s e g 1 4 s e g 1 5 p 3 5 / s e g 2 3 p 3 6 / s e g 2 4 p 3 7 / s e g 2 5 p 0 0 / s e g 2 6 p 0 1 / s e g 2 7 p 0 2 / s e g 2 8 p 0 3 / s e g 2 9 p 0 4 / s e g 3 0 p 0 5 / s e g 3 1 p 0 6 / s e g 3 2 p 0 7 / s e g 3 3 p 1 0 / s e g 3 4 p 1 1 / s e g 3 5 p 1 2 / s e g 3 6 p 1 3 / s e g 3 7 p 1 4 / s e g 3 8 p 1 5 / s e g 3 9 c 1 v l 1 p 6 7 / a n 7 p 6 6 / a n 6 p 6 5 / a n 5 p 6 4 / a n 4 p 6 2 / s c l k 2 1 / a n 2 p 6 1 / s o u t 2 / a n 1 p 6 0 / s i n 2 / a n 0 p 5 7 / a d t / d a 2 p 5 6 / d a 1 p 5 5 / c n t r 1 p 5 4 / c n t r 0 p 5 3 / r t p 1 p 5 2 / r t p 0 p 5 1 / p w m 1 p 5 0 / p w m 0 p 4 6 / s c l k 1 p 4 5 / t x d p 4 4 / r x d p 4 3 / / t o u t p 4 2 / i n t 2 p 4 1 / i n t 1 p 4 0 p 7 7 p 7 6 p 7 5 p 7 4 c 2 v l 2 v l 3 c o m 0 c o m 1 c o m 2 v r e f a v s s v c c s e g 8 s e g 0 s e g 1 s e g 2 s e g 4 s e g 5 s e g 6 s e g 7 s e g 3 p 7 2 p 7 3 p 7 1 p 7 0 / i n t 0 x cin x cout x in x out v ss p 2 7 p 2 6 p2 5 p 2 4 p2 3 p 2 1 p 1 6 p 2 2 p 2 0 p 1 7 r e s e t s e g 1 6 s e g 1 7 c o m 3 p 4 7 / s r d y 1 p 6 3 / s c l k 2 2 / a n 3
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 2 package type : 100p6q-a pin configuration (top view) fig. 2 pin configuration of m37560mf-xxxgp 1 23 45 678910111 21 31 41 51 61 71 81 92 02 12 22 32 42 5 2 6 2 7 2 8 29 30 31 3 2 33 3 4 35 3 6 3 7 3 8 3 9 4 0 41 42 4 3 4 4 45 4 6 4 7 4 8 4 9 5 0 5 1 52 53 54 55 56 57 58 59 60 6 1 62 63 64 65 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 0 0 1 m37560mf- xxx gp s e g 1 2 s e g 1 1 s e g 1 0 s e g 9 s e g 8 s e g 7 s e g 6 seg 5 s e g 4 s e g 3 seg 2 seg 1 s e g 0 v cc v ref av ss c o m 3 c o m 2 com 1 com 0 v l 3 v l2 c 2 c 1 v l 1 p 6 7 / a n 7 p 6 6 / a n 6 p 6 5 / a n 5 p 6 4 / a n 4 p 5 7 / a d t / d a 2 p 5 6 / d a 1 p 5 5 / c n t r 1 p 5 4 / c n t r 0 p 4 1 / i n t 1 p 4 0 p 4 3 / / t o u t p 5 3 / r t p 1 p 5 2 / r t p 0 p 5 1 / p w m 1 p 5 0 / p w m 0 p 7 7 p 4 2 / i n t 2 p7 2 p7 3 p7 1 p7 0 /int 0 x cin x cout x in x out v ss p2 7 p2 6 p2 5 p2 4 p2 3 p2 1 p1 6 p2 2 p2 0 p1 7 reset p7 6 p7 5 p7 4 p1 5 /seg 39 p1 4 /seg 38 p 3 1 / s e g 1 9 p 3 0 / s e g 1 8 p 3 2 / s e g 2 0 p 3 3 / s e g 2 1 p 3 4 / s e g 2 2 s e g 1 3 s e g 1 4 s e g 1 5 p 3 5 / s e g 2 3 p 3 6 / s e g 2 4 p 3 7 / s e g 2 5 p 0 0 / s e g 2 6 p 0 1 / s e g 2 7 p 0 2 / s e g 2 8 p 0 3 / s e g 2 9 p 0 4 / s e g 3 0 p 0 5 / s e g 3 1 p 0 6 / s e g 3 2 p 0 7 / s e g 3 3 p 1 0 / s e g 3 4 p 1 1 / s e g 3 5 p 1 2 / s e g 3 6 p 1 3 / s e g 3 7 s e g 1 6 s e g 1 7 p 6 2 / s c l k 2 1 / a n 2 p 6 1 / s o u t 2 / a n 1 p 6 0 / s i n 2 / a n 0 p 6 3 / s c l k 2 2 / a n 3 p 4 6 / s c l k 1 p 4 5 / t x d p 4 4 / r x d p 4 7 / s r d y 1
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 3 functional block diagram (package : 100p6s-a) fig. 3 functional block diagram i n t 1 , i n t 2 c n t r 0 , c n t r 1 d a 1 a d t c p u a x y s p c h p c l p s r e s e t v c c v s s ( 5 v ) ( 0 v ) r o m r a m 3 5 9 1 4 0 p 4 ( 8 ) p 2 ( 8 ) p 0 ( 8 ) p 1 ( 8 ) p 6 ( 8 ) p 7 ( 8 ) p 3 ( 8 ) p 5 ( 8 ) 1 2 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 3 6 3 7 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 4 5 6 7 8 9 1 0 9 3 9 2 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 x c i n x c o u t x i n o u t x c o u t x x c i n s i / o 1 ( 8 ) v r e f a v s s v l 1 c 1 c 2 v l 2 v l 3 c o m 0 c o m 1 c o m 2 c o m 3 s e g 0 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 s e g 7 s e g 8 s e g 9 s e g 1 0 s e g 1 1 s e g 1 2 s e g 1 3 s e g 1 4 s e g 1 5 s e g 1 6 s e g 1 7 x c i n c o u t x 3 8 3 9 s i / o 2 ( 8 ) p w m ( 8 ) i n t 0 d - a 2 d - a 1 d a 2 t o u t l c d d r i v e c o n t r o l c i r c u i t l c d d i s p l a y r a m ( 2 0 b y t e s ) t i m e r x ( 1 6 ) t i m e r y ( 1 6 ) t i m e r 1 ( 8 ) t i m e r 2 ( 8 ) t i m e r 3 ( 8 ) d a t a b u s c l o c k g e n e r a t i n g c i r c u i t c l o c k i n p u t c l o c k o u t p u t s u b - c l o c k o u t p u t s u b - c l o c k i n p u t r e s e t k e y i n p u t ( k e y - o n w a k e u p ) i n t e r r u p t r e a l t i m e p o r t f u n c t i o n a - d c o n v e r t e r ( 8 ) i / o p o r t p 0 i / o p o r t p 1 i / o p o r t p 2 i / o p o r t p 4 i / o p o r t p 5 i / o p o r t p 6 o u t p u t p o r t p 3 i / o p o r t p 7 r e s e t i n p u t x c o u t s u b - c l o c k o u t p u t x c i n s u b - c l o c k i n p u t w a t c h d o g t i m e r
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 4 pin description table 1 pin description (1) v cc , v ss function pin name function except a port function lcd segment output pins power source apply voltage of 2.2 v to 5.5 v to v cc , and 0 v to v ss . v ref av ss reset x in x out v l1 v l3 c 1 , c 2 com 0 com 3 seg 0 seg 17 p0 0 /seg 26 p0 7 /seg 33 p1 0 /seg 34 p1 5 /seg 39 p1 6 , p1 7 p2 0 p2 7 p3 0 /seg 18 p3 7 /seg 25 analog refer- ence voltage analog power source reset input clock input clock output lcd power source charge-pump capacitor pin common output segment output i/o port p0 i/o port p1 i/o port p2 output port p3 reference voltage input pin for a-d converter. gnd input pin for a-d converter. connect to v ss . reset input pin for active l . input and output pins for the main clock generating circuit. connect a ceramic resonator or a quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. if an external clock is used, connect the clock source to the x in pin and leave the x out pin open. a feedback resistor is built-in. input 0 v l1 v l2 v l3 voltage. input 0 v l3 voltage to lcd. (0 v l1 v l2 v l3 when a voltage is multiplied.) external capacitor pins for a voltage multiplier (3 times) of lcd contorl. lcd common output pins. com 2 and com 3 are not used at 1/2 duty ratio. com 3 is not used at 1/3 duty ratio. lcd segment output pins. 8-bit i/o port. cmos compatible input level. cmos 3-state output structure. pull-up control is enabled. i/o direction register allows each 8-bit pin to be pro- grammed as either input or output. 6-bit i/o port with same function as port p0. cmos compatible input level. cmos 3-state output structure. pull-up control is enabled. i/o direction register allows each 6-bit pin to be pro- grammed as either input or output. 2-bit i/o port. cmos compatible input level. cmos 3-state output structure. i/o direction register allows each pin to be individually programmred as either input or output. pull-up control is enabled. 8-bit i/o port with same function as p1 6 and p1 7 . cmos compatible input level. cmos 3-state output structure. pull-up control is enabled. 8-bit output port with same function as port p0. cmos 3-state output structure. port output control is enabled. key input (key-on wake-up) interrupt input pins lcd segment output pins
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 5 table 2 pin description (2) function pin name function except a port function p4 0 p4 1 /int 1 , p4 2 /int 2 p4 3 / /t out p4 4 /r x d, p4 5 /t x d, p4 6 /s clk1 , p4 7 /s rdy1 p5 0 /pwm 0 , p5 1 /pwm 1 p5 2 /rtp 0 , p5 3 /rtp 1 p5 4 /cntr 0 , p5 5 /cntr 1 p5 6 /da 1 , p5 7 /adt/da 2 p6 0 /an 0 /s in2, p6 1 /an 1 /s out2, p6 2 /an 2 /s clk21, p6 3 /an 3 /s clk22 p6 4 /an 4 p6 7 /an 7 p7 0 /int 0 p7 1 p7 7 x cout x cin i/o port p4 i/o port p5 i/o port p6 input port p7 i/o port p7 sub-clock output sub-clock input 1-bit i/o port with same function as p1 6 and p1 7 . cmos compatible input level. n-channel open-drain output structure. 7-bit i/o port with same function as p1 6 and p1 7 . cmos compatible input level. cmos 3-state output structure. pull-up control is enabled. 8-bit i/o port with same function as p1 6 and p1 7 . cmos compatible input level. cmos 3-state output structure. pull-up control is enabled. 8-bit i/o port with same function as p1 6 and p1 7 . cmos compatible input level. cmos 3-state output structure. pull-up control is enabled. 1-bit input port. 7-bit i/o port with same function as p1 6 and p1 7 . cmos compatible input level. n-channel open-drain output structure. sub-clock generating circuit i/o pins. (connect a resonator. external clock cannot be used.) interrupt input pins clock output pin timer 2 output pin serial i/o1 i/o pins pwm function pins real time port function pins timer x, y function pins d-a conversion output pins a-d conversion input pins serial i/o2 i/o pins a-d conversion input pins interrupt input pin
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 6 part numbering fig. 4 part numbering m 3 7 5 6 0 m f x x x f p p r o d u c t rom/prom s i ze 1 2 3 4 5 6 7 8 9 a b c d e f : 4096 b ytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes : 36864 bytes : 40960 bytes : 45056 bytes : 49152 bytes : 53248 bytes : 57344 bytes : 61440 bytes th e fi rst 128 b ytes an d t h e l ast 2 b ytes o f rom are reserved areas ; they cannot be used. m emory type m : m as k rom vers i on r o m n u m b e r p ac k age type fp gp : 100p6s-a package : 100p6q-a package
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 7 group expansion mitsubishi plans to expand the 7560 group as follows. memory type support for mask rom version. memory size rom size ........................................................... 32 k to 60 k bytes ram size .......................................................... 1024 to 2560 bytes packages 100p6q-a .................................. 0.5 mm-pitch plastic molded qfp 100p6s-a ................................ 0.65 mm-pitch plastic molded qfp memory expansion plan fig. 5 memory expansion plan rom size (bytes) ram size (bytes) 2 5 65 1 27 6 81 0 2 41 2 8 01 5 3 61 7 9 2 192 2 0 4 8 2304 2560 32k 28k 24k 20k 16k 1 2 k 8 k 4k 52k 4 8 k 4 4 k 4 0 k 3 6 k 56k 60k m 3 7 5 6 0 m f under development m37560m8 under development currently products are listed below. table 3. list of products as of mar. 2001 remarks mask rom version mask rom version mask rom version mask rom version package 100p6s-a 100p6q-a 100p6s-a 100p6q-a product m37560m8-xxxfp m37560m8-xxxgp m37560mf-xxxfp m37560mf-xxxgp ram size (bytes) 1024 32768 (32638) 61440 (61310) rom size (bytes) rom size for user in ( ) 2560
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 8 functional description central processing unit (cpu) the 7560 group uses the standard 740 family instruction set. re- fer to the table of 740 family addressing modes and machine instructions or the 740 family software manual for details on the instruction set. machine-resident 740 family instructions are as follows: the fst and slw instruction cannot be used. the stp, wit, mul, and div instruction can be used. [accumulator (a)] the accumulator is an 8-bit register. data operations such as data transfer, etc., are executed mainly through the accumulator. [index register x (x)] the index register x is an 8-bit register. in the index addressing modes, the value of the operand is added to the contents of register x and specifies the real address. [index register y (y)] the index register y is an 8-bit register. in partial instruction, the value of the operand is added to the contents of register y and specifies the real address. [stack pointer (s)] the stack pointer is an 8-bit register used during subroutine calls and interrupts. this register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. the low-order 8 bits of the stack address are determined by the contents of the stack pointer. the high-order 8 bits of the stack address are determined by the stack page selection bit. if the stack page selection bit is 0 , the high-order 8 bits becomes 00 16 . if the stack page selection bit is 1 , the high-order 8 bits becomes 01 16 . the operations of pushing register contents onto the stack and popping them from the stack are shown in figure 7. store registers other than those described in figure 7 with pro- gram when the user needs them during interrupts or subroutine calls. [program counter (pc)] the program counter is a 16-bit counter consisting of two 8-bit registers pc h and pc l . it is used to indicate the address of the next instruction to be executed. fig. 6 740 family cpu register structure a accumulator b7 b7 b7 b7 b0 b7 b15 b0 b7 b0 b0 b0 b0 x index register x y index register y s stack pointer pc l program counter pc h n v t b d i z c processor status register (ps) carry flag zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 9 table 4 push and pop instructions of accumulator or processor status register accumulator processor status register push instruction to stack pha php pop instruction from stack pla plp fig. 7 register push and pop at interrupt generation and subroutine call n o t e : c o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t i n t e r r u p t e n a b l e f l a g i s 1 execute jsr on-going routin e m ( s )( p c h ) (s) (s) 1 m ( s )( p c l ) e x e c u t e r t s ( p c l )m ( s ) ( s ) ( s ) 1 ( s ) ( s ) + 1 (s) (s) + 1 ( p c h )m ( s ) s u b r o u t i n e p o p re t u r n a d d r e s s f r o m s t a c k p u s h r e t u r n a d d r e s s o n s t a c k m (s) (ps) e x e c u t e r t i ( p s )m ( s ) ( s ) ( s ) 1 (s) (s) + 1 i n t e r r u p t s e r v i c e r o u t i n e pop contents of processor status register from stack m (s) (pc h ) (s) (s) 1 m ( s )( p c l ) ( s ) ( s ) 1 ( p c l )m ( s ) (s) (s) + 1 (s) (s) + 1 (pc h )m (s) p o p r e t u r n a d d r e s s f r o m s t a c k i f l a g i s s e t f r o m 0 t o 1 f e t c h t h e j u m p v e c t o r p u s h r e t u r n a d d r e s s o n s t a c k p u s h c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r o n s t a c k i n t e r r u p t r e q u e s t ( n o t e ) interrupt disable flag is 0
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 10 [processor status register (ps)] the processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide mcu operation. branch opera- tions can be performed by testing the carry (c) flag , zero (z) flag, overflow (v) flag, or the negative (n) flag. in decimal mode, the z, v, n flags are not valid. bit 0: carry flag (c) the c flag contains a carry or borrow generated by the arith- metic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. bit 1: zero flag (z) the z flag is set if the result of an immediate arithmetic operation or a data transfer is 0 , and cleared if the result is anything other than 0 . bit 2: interrupt disable flag (i) the i flag disables all interrupts except for the interrupt gener- ated by the brk instruction. interrupts are disabled when the i flag is 1 . bit 3: decimal mode flag (d) the d flag determines whether additions and subtractions are executed in binary or decimal. binary arithmetic is executed when this flag is 0 ; decimal arithmetic is executed when it is 1 . decimal correction is automatic in decimal mode. only the adc and sbc instructions can be used for decimal aritmetic. bit 4: break flag (b) the b flag is used to indicate that the current interrupt was gen- erated by the brk instruction. the brk flag in the processor status register is always 0 . when the brk instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to 1 . bit 5: index x mode flag (t) when the t flag is 0 , arithmetic operations are performed be- tween accumulator and memory. when the t flag is 1 , direct arithmetic operations and direct data transfers are enabled be- tween memory locations. bit 6: overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds +127 to -128. when the bit instruction is executed, bit 6 of the memory location op- erated on by the bit instruction is stored in the overflow flag. bit 7: negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. table 5 set and clear instructions of each bit of processor status register set instruction clear instruction c flag sec clc z flag i flag sei cli d flag sed cld b flag t flag set clt v flag clv n flag
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 11 [cpu mode register (cpum)] 003b 16 the cpu mode register contains the stack page selection bit and the internal system clock selection bit. the cpu mode register is allocated at address 003b 16 . fig. 8 structure of cpu mode register n ot ava il a bl e p rocessor mo d e bi ts b1 b0 0 0 : single-chip mode 0 1 : 1 0 : 1 1 : stack page selection bit 0 : 0 page 1 : 1 page not used (returns 1 when read) (do not write 0 to this bit) port x c switch bit 0 : oscillation stop 1 : x cin x cout oscillating function main clock (x in x out ) stop bit 0 : oscillating 1 : stopped main clock division ratio selection bit 0 : f(x in )/2 (high-speed mode) 1 : f(x in )/8 (middle-speed mode) internal system clock selection bit 0 : x in x out selected (middle-/high-speed mode) 1 : x cin x cout selected (low-speed mode) cpu mo d e reg i ster ( c p u m ( c m ) : a d d r e s s 0 0 3 b 1 6 ) b 7 b 0
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 12 memory special function register (sfr) area the special function register area in the zero page contains con- trol registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is user area for storing programs. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page the 256 bytes from addresses 0000 16 to 00ff 16 are called the zero page area. the internal ram and the special function regis- ters (sfr) are allocated to this area. the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area with only 2 bytes is possible in the zero page addressing mode. special page the 256 bytes from addresses ff00 16 to ffff 16 are called the special page area. the special page addressing mode can be used to specify memory addresses in the special page area. ac- cess to this area with only 2 bytes is possible in the special page addressing mode. fig. 9 memory map diagram 1 9 2 2 5 6 3 8 4 5 1 2 6 4 0 7 6 8 8 9 6 1 0 2 4 1 5 3 6 2 0 4 8 2 5 6 0 00 ff 16 013f 16 01bf 16 023f 16 02bf 16 033f 16 03bf 16 043f 16 063f 16 083f 16 0a3f 16 ram area ram s i ze (bytes) add ress xxxx 16 409 6 819 2 1228 8 1638 4 2048 0 2457 6 2867 2 3276 8 3686 4 4096 0 4505 6 4915 2 5324 8 5734 4 6144 0 f 000 16 e000 16 d000 16 c000 16 b000 16 a000 16 9000 16 8000 16 7000 16 6000 16 5000 16 4000 16 3000 16 2000 16 1000 16 f 080 16 e080 16 d080 16 c080 16 b080 16 a080 16 9080 16 8080 16 7080 16 6080 16 5080 16 4080 16 3080 16 2080 16 1080 16 rom area rom s i ze (bytes) add ress yyyy 16 add ress zzzz 16 0 1 0 0 1 6 0 0 0 0 1 6 0040 16 0440 16 f f 0 0 1 6 ffdc 16 fffe 16 ffff 16 xxxx 16 yyyy 16 zzzz 16 ram r o m 0054 16 r eserve d area sfr area n ot use d (n ote ) i nterrupt vector are a r eserve d rom area (128 bytes) z e r o p a g e s p e c i a l p a g e lcd di sp l ay ram area r eserve d rom area n ote: wh en ram area excee d s 1024 b ytes, t h e areas s h own t h e ta bl e are use d .
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 13 fig. 10 memory map of special function register (sfr) 0 0 2 0 1 6 0021 16 0022 16 0 0 2 3 1 6 0 0 2 4 1 6 0 0 2 5 1 6 0 0 2 6 1 6 0 0 2 7 1 6 0 0 2 8 1 6 0 0 2 9 1 6 002 a 16 002 b 16 0 0 2 c 1 6 0 0 2 d 1 6 002 e 16 002 f 16 0030 16 0 0 3 1 1 6 0 0 3 2 1 6 0 0 3 3 1 6 0034 16 0035 16 0036 16 0037 16 0 0 3 8 1 6 0 0 3 9 1 6 003 a 16 003 b 16 003 c 16 003 d 16 003 e 16 003 f 16 0 0 0 0 1 6 0001 16 0002 16 0 0 0 3 1 6 0 0 0 4 1 6 0 0 0 5 1 6 0 0 0 6 1 6 0 0 0 7 1 6 0 0 0 8 1 6 0 0 0 9 1 6 000 a 16 000 b 16 0 0 0 c 1 6 0 0 0 d 1 6 0 0 0 e 1 6 000 f 16 0010 16 0 0 1 1 1 6 0 0 1 2 1 6 0 0 1 3 1 6 0014 16 0015 16 0016 16 0017 16 0 0 1 8 1 6 0 0 1 9 1 6 001 a 16 001 b 16 001 c 16 001 d 16 001 e 16 0 0 1 f 1 6 p o r t p 0 ( p 0 ) p ort p 1 (p 1 ) p o r t p 1 d i r e c t i o n r e g i s t e r ( p 1 d ) p o r t p 2 ( p 2 ) p o r t p 2 d i r e c t i o n r e g i s t e r ( p 2 d ) p o r t p 3 ( p 3 ) p o r t p 4 ( p 4 ) p o r t p 4 d i r e c t i o n r e g i s t e r ( p 4 d ) p ort p 5 (p 5 ) p ort p 5 di rect i on reg i ster (p 5 d) p o r t p 6 ( p 6 ) p o r t p 6 d i r e c t i o n r e g i s t e r ( p 6 d ) p o r t p 7 ( p 7 ) p o r t p 7 d i r e c t i o n r e g i s t e r ( p 7 d ) s er i a l i / o 1 status reg i ster (sio 1 sts) s er i a l i / o 1 contro l reg i ster (sio 1 con) uart contro l reg i ster (uartcon) b a u d r a t e g e n e r a t o r ( b r g ) i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) t i m e r 3 ( t 3 ) ti mer x mo d e reg i ster (txm) i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( i n t e d g e ) cpu mo d e reg i ster (cpum) i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) t i m e r x ( l o w ) ( t x l ) t i m e r y ( l o w ) ( t y l ) t i m e r 1 ( t 1 ) t i m e r 2 ( t 2 ) t i m e r x ( h i g h ) ( t x h ) ti mer y (hi g h) (tyh) pull reg i ster a (pulla) p u l l r e g i s t e r b ( p u l l b ) ti mer y mo d e reg i ster (tym) ti mer 123 mo d e reg i ster (t 123 m) t out / output contro l reg i ster (ckout) s egment output ena bl e reg i ster (seg) l c d m o d e r e g i s t e r ( l m ) a - d contro l reg i ster (adcon) a - d convers i on reg i ster (ad) t ransm i t/ r ece i ve b u ff er reg i ster (tb / rb) r e s e r v e d a r e a k ey i nput contro l reg i ster (kic) p o r t p 0 d i r e c t i o n r e g i s t e r ( p 0 d ) p o r t p 3 o u t p u t c o n t r o l r e g i s t e r ( p 3 c ) r e s e r v e d a r e a s er i a l i / o 2 contro l reg i ster (sio 2 con) s e r i a l i / o 2 r e g i s t e r ( s i o 2 ) pwm contro l reg i ster (pwmcon) p w m p r e s c a l e r ( p r e p w m ) p w m r e g i s t e r ( p w m ) r e s e r v e d a r e a r e s e r v e d a r e a r e s e r v e d a r e a r eserve d area d - a 1 convers i on reg i ster (da 1 ) d - a 2 convers i on reg i ster (da 2 ) d - a c o n t r o l r e g i s t e r ( d a c o n ) w a t c h d o g t i m e r c o n t r o l r e g i s t e r ( w d t c o n )
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 14 i/o ports direction registers the i/o ports (ports p0, p1, p2, p4, p5, p6, p7 1 p7 7 ) have direc- tion registers which determine the input/output direction of each individual pin. (ports p0 0 p0 7 are shared with bit 0 of the port p0 direction register, and ports p1 0 p1 5 shared with bit 0 of the port p1 direction register.) each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. when 0 is written to the bit corresponding to a pin, that pin be- comes an input pin. when 1 is written to that bit, that pin be- comes an output pin. if data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. pins set to input are floating. if a pin set to input is written to, only the port output latch is written to and the pin remains floating. port p3 output control register bit 0 of the port p3 output control register (address 0007 16 ) en- ables control of the output of ports p3 0 p3 7 . when the bit is set to 1 , the port output function is valid. when resetting, bit 0 of the port p3 output control register is set to 0 (the port output function is invalid) and pulled up. pull-up control by setting the pull register a (address 0016 16 ) or the pull reg- ister b (address 0017 16 ), ports p0 to p2, p4 to p6 can control pull- up with a program. however, the contents of pull register a and pull register b do not affect ports programmed as the output ports. the pull register a setting is invalid for pins set to segment out- put with the segment output enable register. fig. 11 structure of pull register a and pull register b p 0 0 , p 0 1 pu ll -up p0 2 , p0 3 pull-up p0 4 p0 7 pull-up p1 0 p1 3 pull-up p1 4 , p1 5 pull-up p1 6 , p1 7 pull-up p2 0 p2 3 pull-up p2 4 p2 7 pull-up p u l l r e g i s t e r a ( p u l l a : a d d r e s s 0 0 1 6 1 6 ) b 7 b 0 p 4 1 p 4 3 pu ll -up p4 4 p4 7 pull-up p5 0 p5 3 pull-up p5 4 p5 7 pull-up p6 0 p6 3 pull-up p6 4 p6 7 pull-up not used (return 0 when read) 0 : d i s a b l e 1 : e n a b l e pull reg i ster b (pullb : address 0017 16 ) b 7 b 0 n ote: th e contents o f pull reg i ster a an d pull reg i ster b do not affect ports programmed as the output port.
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 15 pwm output da 2 output a-d trigger input da 1 output diagram no. related sfrs input/output name pin non-port function i/o format table 6 list of i/o port function (1) p0 0 /seg 26 p0 7 /seg 33 p1 0 /seg 34 p1 5 /seg 39 p1 6 , p1 7 p2 0 p2 7 p3 0 /seg 18 p3 7 /seg 25 p4 0 p4 1 /int 1 , p4 2 /int 2 p4 3 / /t out p4 4 /r x d, p4 5 /t x d, p4 6 /s clk1 , p4 7 /s rdy1 p5 0 /pwm 0 , p5 1 /pwm 1 p5 2 /rtp 0 , p5 3 /rtp 1 p5 4 /cntr 0 p5 5 /cntr 1 p5 6 /da 1 p5 7 /adt/ da 2 port p0 port p1 port p2 port p3 port p4 port p5 input/output, byte unit input/output, 6-bit unit input/output, individual bits input/output, individual bits output input/output, individual bits input/output, individual bits cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos 3-state output cmos compatible input level n-channel open-drain output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output lcd segment output lcd segment output key input (key-on wake-up) interrupt input lcd segment output external interrupt input timer output output serial i/o1 function i/o real time port function output timer x function i/o timer y function input pull register a segment output enable register pull register a segment output enable register pull register a pull register a interrupt control register2 key input control register segment output enable register interrupt edge selection register pull register b timer 123 mode register t out / output control register pull register b serial i/o1 control register serial i/o1 status register uart control register pull register b pwm control register pull register b timer x mode register pull register b timer x mode register pull register b timer y mode register pull register b d-a control register pull register b d-a control register a-d control register (1) (2) (1) (2) (4) (3) (13) (4) (12) (5) (6) (7) (8) (10) (9) (11) (14) (15) (15) p3 output enable register
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 16 pin name i/o format non-port function related sfr s diagram no. input/output notes1: how to use double-function ports as function i/o ports, refer to the applicable sections. 2: make sure that the input level at each pin is either 0 v or v cc during execution of the stp instruction. when an input level is at an intermediate po- tential, a current will flow v cc to v ss through the input-stage gate. table 7 list of i/o port function (2) p6 0 /s in2 /an 0 p6 1 /s out2 / an 1 p6 2 /s clk21 / an 2 p6 3 /s clk22 / an 3 p6 4 /an 4 p6 7 /an 7 p7 0 /int 0 p7 1 p7 7 com 0 com 3 seg 0 seg 17 port p6 port p7 common segment input/ output, individual bits input input/ output, individual bits output output cmos compatible input level cmos 3-state output cmos compatible input level cmos compatible input level n-channel open-drain output lcd common output lcd segment output a-d conversion input serial i/o2 function i/o a-d conversion input external interrupt input pull register b a-d control register serial i/o2 control register a-d control register pull register b interrupt edge selection register (17) (18) (19) (20) (16) (23) (13) (21) (22) lcd mode register
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 17 fig. 12 port block diagram (1) (5) port p4 4 ( 4 ) p o r t s p 1 6 , p 1 7 , p 2 , p 4 1 , p 4 2 pull-up control v l 1 / v s s v l2 /v l3 /v cc v l1 /v ss v l2 /v l3 /v cc v l1 /v ss v l 2 / v l 3 / v c c ( 1 ) p o r t s p 0 1 p 0 7 , p 1 1 p 1 5 d a t a b u s p o r t l a t c h i n t e r f a c e l o g i c l e v e l s h i f t c i r c u i t p u l l - u p p o r t s e g m e n t s e g m e n t / p o r t l c d d r i v e t i m i n g p o r t / s e g m e n t s e g m e n t d a t a port direction register p o r t d i r e c t i o n r e g i s t e r (2) ports p0 0 , p1 0 d a t a b u sp o r t l a t c h interface logic level shift circuit port segment s e g m e n t / p o r t lcd drive timing port/segment s e g m e n t d a t a port direction register d i r e c t i o n r e g i s t e r pull-up d a t a b u s port latch i n t e r f a c e l o g i c l e v e l s h i f t c i r c u i t p o r t s e g m e n t segment/port lcd drive timing port/segment segment data output control pull-up ( 3 ) p o r t p 3 d a t a b u s port latch d i r e c t i o n r e g i s t e r key-on wake up interrupt input int 1 , int 2 interrupt input e x c e p t p 1 6 , p 1 7 p u l l - u p c o n t r o l data bus port latch d i r e c t i o n r e g i s t e r s e r i a l i / o 1 e n a b l e b i t s e r i a l i / o 1 i n p u t r e c e p t i o n e n a b l e b i t
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 18 fig. 13 port block diagram (2) ( 6 ) p o r t p 4 5 ( 7 ) p o r t p 4 6 ( 8 ) p o r t p 4 7 ( 9 ) p o r t s p 5 2 , p 5 3 (10) ports p5 0 ,p5 1 p w m f u n c t i o n e n a b l e b i t p w m o u t p u t ( 1 1 ) p o r t p 5 4 pulse output mode timer output cntr 0 interrupt input p u l l - u p c o n t r o l d i r e c t i o n r e g i s t e r d a t a b u s p o r t l a t c h s e r i a l i / o 1 o u t p u t p 4 5 / t x d p - c h a n n e l o u t p u t d i s a b l e b i t s e r i a l i / o 1 e n a b l e b i t t r a n s m i s s i o n e n a b l e b i t serial i/o1 clock output d i r e c t i o n r e g i s t e r data bus p o r t l a t c h p u l l - u p c o n t r o l s e r i a l i / o 1 e n a b l e b i t s e r i a l i / o 1 c l o c k i n p u t serial i/o1 synchronization clock selection bit serial i/o1 mode selection bit serial i/o1 enable bit p u l l - u p c o n t r o l s e r i a l i / o 1 m o d e s e l e c t i o n b i t s e r i a l i / o 1 e n a b l e b i t s r d y 1 o u t p u t e n a b l e b i t d i r e c t i o n r e g i s t e r data bus port latch serial i/o1 ready output d i r e c t i o n r e g i s t e r data bus port latch pull-up control real time control bit real time port data p u l l - u p c o n t r o l direction register data bus port latch pull-up control d i r e c t i o n r e g i s t e r d a t a b u s p o r t l a t c h
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 19 fig. 14 port block diagram (3) ( 1 2 ) p o r t p 4 3 t out / output control timer output o u t p u t t o u t / s e l e c t i o n b i t ( 1 3 ) p o r t s p 4 0 , p 7 1 p 7 7 ( 1 4 ) p o r t p 5 5 c n t r 1 i n t e r r u p t i n p u t (15) ports p5 6 ,p5 7 a - d t r i g g e r i n p u t d - a c o n v e r t e r o u t p u t e x c e p t p 5 6 ( 1 6 ) p o r t s p 6 4 p 6 7 (17) port p6 0 analog input pin selection bit a-d conversion input s e r i a l i / o 2 i n p u t d-a 1 ,d-a 2 output enable bit d i r e c t i o n r e g i s t e r p o r t l a t c h d a t a b u s p u l l - u p c o n t r o l direction register p o r t l a t c h data bus direction register p o r t l a t c h data bus p u l l - u p c o n t r o l d i r e c t i o n r e g i s t e r port latch d a t a b u s p u l l - u p c o n t r o l d i r e c t i o n r e g i s t e r port latch data bus pull-up control analog input pin selection bit a - d c o n v e r s i o n i n p u t d i r e c t i o n r e g i s t e r p o r t l a t c h data bus pull-up control
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 20 fig. 15 port block diagram (4) ( 1 8 ) p o r t p 6 1 (19) port p6 2 ( 2 0 ) p o r t p 6 3 s e r i a l i / o 2 o u t p u t s e r i a l i / o 2 t r a n s m i t e n d s i g n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s e r i a l i / o 2 p o r t s e l e c t i o n b i t pull-up control analog input pin selection bit a - d c o n v e r s i o n i n p u t p6 1 /s out2 p-channel output disable bit (21)com 0 com 3 ( 2 2 ) s e g 0 s e g 1 7 v l 3 v l 2 v l1 v ss v l2 /v l3 v l 1 / v s s ( 2 3 ) p o r t p 7 0 i n t 0 i n p u t s y n c h r o n o u s c l o c k s e l e c t i o n b i t s e r i a l i / o 2 c l o c k o u t p u t s e r i a l i / o 2 c l o c k i n p u t serial i/o2 port selection bit synchronous clock output pin selection bit a-d conversion input s e r i a l i / o 2 c l o c k o u t p u t a-d conversion input d i r e c t i o n r e g i s t e r port latch d a t a b u s pull-up control d i r e c t i o n r e g i s t e r port latch d a t a b u s analog input pin selection bit pull-up control direction register p o r t l a t c h d a t a b u s analog input pin selection bit synchronous clock selection bit serial i/o2 port selection bit synchronous clock output pin selection bit direction register port latch data bus the gate input signal of each transistor is controlled by the lcd duty ratio and the bias value. t h e v o l t a g e a p p l i e d t o t h e s o u r c e s o f p - c h a n n e l a n d n - c h a n n e l t r a n s i s t o r s i s t h e c o n t r o l l e d v o l t a g e b y t h e b i a s v a l u e .
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 21 interrupts i nterrupts occur by seventeen sources: seven external, nine inter- nal, and one software. interrupt control each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software in- terrupt set by the brk instruction. an interrupt occurs if the corre- sponding interrupt request and enable bits are 1 and the inter- rupt disable flag is 0 . interrupt enable bits can be set or cleared by software. interrupt request bits can be cleared by software, but cannot be set by software. the brk instruction cannot be disabled with any flag or bit. the i flag disables all interrupts except the brk instruction interrupt. when several interrupts occur at the same time, the interrupts are received according to priority. interrupt operation by acceptance of an interrupt, the following operations are auto- matically performed: 1. the contents of the program counter and the processor status register are automatically pushed onto the stack. 2. the interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. the interrupt jump destination address is read from the vector table into the program counter. notes1: vector addresses contain interrupt jump destination addresses. 2: reset function in the same way as an interrupt with the highest priority. table 8 interrupt vector addresses and priority remarks interrupt request generating conditions at reset at detection of either rising or falling edge of int 0 input at detection of either rising or falling edge of int 1 input at completion of serial i/o1 data reception at completion of serial i/o1 transmit shift or when transmis- sion buffer is empty interrupt source low high priority vector addresses (note 1) reset (note 2) int 0 int 1 serial i/o1 reception serial i/o1 transmission timer x timer y timer 2 timer 3 cntr 0 cntr 1 timer 1 int 2 serial i/o2 key input (key-on wake-up) adt a-d conversion brk instruction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 at timer x underflow at timer y underflow at timer 2 underflow at timer 3 underflow at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of cntr 1 input at timer 1 underflow at detection of either rising or falling edge of int 2 input at completion of serial i/o2 data transmission or reception at falling of conjunction of input level for port p2 (at input mode) at falling edge of adt input at completion of a-d conversion at brk instruction execution non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) valid when serial i/o1 is selected valid when serial i/o1 is selected external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) valid when serial i/o2 is selected external interrupt (valid at falling) valid when adt interrupt is selected external interrupt (valid at falling) valid when a-d interrupt is selected non-maskable software interrupt
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 22 fig. 16 interrupt control fig. 17 structure of interrupt-related registers notes on interrupts when setting the followings, the interrupt request bit may be set to 1 . when setting external interrupt active edge related register: interrupt edge selection register (address 3a 16 ) timer x mode register (address 27 16 ) timer y mode register (address 28 16 ) when switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated related register: interrupt source selection bit of a-d control regsiter (bit 6 of address 34 16 ) when not requiring for the interrupt occurrence synchronous with these setting, take the following sequence. ? set the corresponding interrupt enable bit to 0 (disabled). ? set the interrupt edge select bit (polarity switch bit) or the inter- rupt source select bit to 1 . ? set the corresponding interrupt request bit to 0 after 1 or more instructions have been executed. ? set the corresponding interrupt enable bit to 1 (enabled). interrupt request bi t interrupt enable bi t interrupt disable flag (i) brk instruction rese t i n t e r r u p t r e q u e s t b 7 b 0 i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r i n t 0 i n t e r r u p t e d g e s e l e c t i o n b i t i n t 1 i n t e r r u p t e d g e s e l e c t i o n b i t i n t 2 i n t e r r u p t e d g e s e l e c t i o n b i t n o t u s e d ( r e t u r n 0 w h e n r e a d ) (intedge : a dd ress 003 a 16 ) i n t e r r u p t r e q u e s t r e g i s t e r 1 i n t 0 i n t e r r u p t r e q u e s t b i t i n t 1 i n t e r r u p t r e q u e s t b i t s e r i a l i / o 1 r e c e i v e i n t e r r u p t r e q u e s t b i t s e r i a l i / o 1 t r a n s m i t i n t e r r u p t r e q u e s t b i t t i m e r x i n t e r r u p t r e q u e s t b i t t i m e r y i n t e r r u p t r e q u e s t b i t t i m e r 2 i n t e r r u p t r e q u e s t b i t t i m e r 3 i n t e r r u p t r e q u e s t b i t i n t e r r u p t c o n t r o l r e g i s t e r 1 int 0 i nterrupt ena bl e bi t int 1 interrupt enable bit serial i/o1 receive interrupt enable bit serial i/o1 transmit interrupt enable bit timer x interrupt enable bit timer y interrupt enable bit timer 2 interrupt enable bit timer 3 interrupt enable bit 0 : n o i nterrupt request i ssue d 1 : interrupt request issued (ireq 1 : a dd ress 003 c 16 ) (icon 1 : a dd ress 003 e 16 ) i nterrupt request reg i ster 2 c n t r 0 i n t e r r u p t r e q u e s t b i t c n t r 1 i n t e r r u p t r e q u e s t b i t t i m e r 1 i n t e r r u p t r e q u e s t b i t i n t 2 i n t e r r u p t r e q u e s t b i t s e r i a l i / o 2 i n t e r r u p t r e q u e s t b i t k e y i n p u t i n t e r r u p t r e q u e s t b i t a d t / a d c o n v e r s i o n i n t e r r u p t r e q u e s t b i t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) ( i r e q 2 : a d d r e s s 0 0 3 d 1 6 ) i n t e r r u p t c o n t r o l r e g i s t e r 2 cntr 0 i nterrupt ena bl e bi t cntr 1 interrupt enable bit timer 1 interrupt enable bit int 2 interrupt enable bit serial i/o2 interrupt enable bit key input interrupt enable bit adt/ad conversion interrupt enable bit not used (returns 0 when read) (do not write 1 to this bit) 0 : i n t e r r u p t s d i s a b l e d 1 : i n t e r r u p t s e n a b l e d (icon 2 : a dd ress 003 f 16 ) 0 : f a lli ng e d ge act i ve 1 : rising edge active b 7 b 0 b 7 b 0 b 7 b 0 b 7 b 0
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 23 key input interrupt (key-on wake up) a key-on wake up interrupt request is generated by applying l level voltage to any pin of port p2 that have been set to input mode. in other words, it is generated when and of input level goes from 1 to 0 . an example of using a key input interrupt is shown in figure 18, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports p2 0 p2 3 . fig. 18 connection example when using key input control register, key input interrupt and port p2 block diagram p o r t p 2 0 l a t c h p o r t p 2 0 d i r e c t i o n r e g i s t e r = 0 p o r t p 2 1 l a t c h p o r t p 2 1 d i r e c t i o n r e g i s t e r = 0 port p2 2 latch port p2 2 direction register = 0 p o r t p 2 3 l a t c h p o r t p 2 3 d i r e c t i o n r e g i s t e r = 0 port p2 4 latch p o r t p 2 4 d i r e c t i o n r e g i s t e r = 1 port p2 5 latch port p2 5 direction register = 1 port p2 6 latch port p2 6 direction register = 1 p o r t p 2 7 l a t c h p o r t p 2 7 d i r e c t i o n r e g i s t e r = 1 p 2 0 i n p u t p 2 1 i n p u t p2 2 input p 2 3 i n p u t p2 4 output p2 5 output p 2 6 o u t p u t p 2 7 o u t p u t p u l l r e g i s t e r a b i t 2 = 1 port p2 input reading circuit p o r t p x x l l e v e l o u t p u t ? p - c h a n n e l t r a n s i s t o r f o r p u l l - u p ? ? c m o s o u t p u t b u f f e r key input interrupt request key input control register = 1 k e y i n p u t c o n t r o l r e g i s t e r = 1 k e y i n p u t c o n t r o l r e g i s t e r = 1 k e y i n p u t c o n t r o l r e g i s t e r = 1 k e y i n p u t c o n t r o l r e g i s t e r = 1 k e y i n p u t c o n t r o l r e g i s t e r = 1 k e y i n p u t c o n t r o l r e g i s t e r = 1 k e y i n p u t c o n t r o l r e g i s t e r = 1 ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ?
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 24 timers the 7560 group has five timers: timer x, timer y, timer 1, timer 2, and timer 3. timer x and timer y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. all timers are down count timers. when the timer reaches 00 16 , an underflow occurs at the next count pulse and the correspond- ing timer latch is reloaded into the timer and the count is contin- ued. when a timer underflows, the interrupt request bit corre- sponding to that timer is set to 1 . read and write operation on 16-bit timer must be performed for both high- and low-order bytes. when reading a 16-bit timer, read the high-order byte first. when writing to a 16-bit timer, write the low-order byte first. the 16-bit timer cannot perform the correct operation when reading during the write operation, or when writing during the read operation. fig. 19 timer block diagram 1 p 5 5 / c n t r 1 0 "10 " " 0 0 " , " 0 1 " , " 1 1 " p5 4 /cntr 0 q q t s 0 1 0 q d 0 q d 1 0 1 "10" q q t s 0 1 0 1 1 p 4 3 / / t o u t x cin 0 1 c n t r 0 a c t i v e e d g e s w i t c h b i t t i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t real time port control bit 0 f ( x i n ) / 1 6 ( f ( x c i n ) / 1 6 w h e n = x c i n / 2 ) c n t r 1 a c t i v e e d g e s w i t c h b i t timer y stop control bit falling edge detection period measurement mode t i m e r y i n t e r r u p t r e q u e s t pulse width hl continuously measurement mode rising edge detection timer y operating mode bits t i m e r x i n t e r r u p t r e q u e s t timer x mode register write signal p 4 3 d i r e c t i o n r e g i s t e r p u l s e o u t p u t m o d e p5 4 latch t i m e r x s t o p c o n t r o l b i t timer x write control bit l a t c h t i m e r x o p e r a t - i n g m o d e b i t s 0 0 , 0 1 , 1 1 pulse width measurement mode cntr 0 active edge switch bit p u l s e o u t p u t m o d e p 5 4 d i r e c t i o n r e g i s t e r t o u t o u t p u t a c t i v e e d g e s w i t c h b i t 0 t i m e r 2 w r i t e c o n t r o l b i t t out output control bit t i m e r 3 c o u n t s o u r c e s e l e c t i o n b i t timer 2 interrupt request t i m e r 3 i n t e r r u p t r e q u e s t t i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t t i m e r 1 i n t e r r u p t r e q u e s t data bus r e a l t i m e p o r t c o n t r o l b i t 1 r e a l t i m e p o r t c o n t r o l b i t 1 timer y (low) (8) timer y (high) (8) timer 3 latch (8) timer 3 (8) t i m e r 1 l a t c h ( 8 ) timer 1 (8) t i m e r 2 l a t c h ( 8 ) timer 2 (8) timer x (low) (8) timer x (high) (8) t i m e r x ( l o w ) l a t c h ( 8 ) timer x (high) latch (8) timer y (low) latch (8) t i m e r y ( h i g h ) l a t c h ( 8 ) l a t c h t out output control bit p 4 3 l a t c h f ( x i n ) / 1 6 ( f ( x c i n ) / 1 6 w h e n = x c i n / 2 ) f(x in )/16 (f(x cin )/16 when = x cin /2) f ( x i n ) / 1 6 ( f ( x c i n ) / 1 6 w h e n = x c i n / 2 ) f(x in )/16 (f(x cin )/16 when = x cin /2) p 5 2 / r t p 0 p 5 3 / r t p 1 p 5 2 d a t a f o r r e a l t i m e p o r t p5 3 data for real time port
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 25 timer x timer x is a 16-bit timer that can be selected in one of four modes and can be controlled the timer x write and the real time port by setting the timer x mode register. (1) timer mode the timer counts f(x in )/16 (or f(x cin )/16 in low-speed mode). (2) pulse output mode each time the timer underflows, a signal output from the cntr 0 pin is inverted. except for this, the operation in pulse output mode is the same as in timer mode. when using a timer in this mode, set the corresponding port p5 4 direction register to output mode. (3) event counter mode the timer counts signals input through the cntr 0 pin. except for this, the operation in event counter mode is the same as in timer mode. when using a timer in this mode, set the corre- sponding port p5 4 direction register to input mode. (4) pulse width measurement mode the count source is f(x in )/16 (or f(x cin )/16 in low-speed mode). if cntr 0 active edge switch bit is 0 , the timer counts while the in- put signal of cntr 0 pin is at h . if it is 1 , the timer counts while the input signal of cntr 0 pin is at l . when using a timer in this mode, set the corresponding port p5 4 direction register to input mode. timer x write control if the timer x write control bit is 0 , when the value is written in the address of timer x, the value is loaded in the timer x and the latch at the same time. if the timer x write control bit is 1 , when the value is written in the address of timer x, the value is loaded only in the latch. the value in the latch is loaded in timer x after timer x underflows. if the value is written in latch only, unexpected value may be set in the high-order counter when the writing in high-order latch and the underflow of timer x are performed at the same timing. real time port control while the real time port function is valid, data for the real time port are output from ports p5 2 and p5 3 each time the timer x underflows. (however, if the real time port control bit is changed from 0 to 1 after set of the real time port data, data are output independent of the timer x operation.) if the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer x. before using this function, set the corresponding port direction registers to output mode. note on cntr 0 interrupt active edge selection cntr 0 interrupt active edge depends on the cntr 0 active edge switch bit. fig. 20 structure of timer x mode register ti mer x mo d e reg i ster (txm : address 0027 16 ) t i m e r x w r i t e c o n t r o l b i t 0 : w r i t e v a l u e i n l a t c h a n d c o u n t e r 1 : w r i t e v a l u e i n l a t c h o n l y r e a l t i m e p o r t c o n t r o l b i t 0 : r e a l t i m e p o r t f u n c t i o n i n v a l i d 1 : r e a l t i m e p o r t f u n c t i o n v a l i d p 5 2 d a t a f o r r e a l t i m e p o r t p 5 3 d a t a f o r r e a l t i m e p o r t t i m e r x o p e r a t i n g m o d e b i t s b 5 b 4 00 : t i m e r m o d e 01 : p u l s e o u t p u t m o d e 10 : e v e n t c o u n t e r m o d e 11 : p u l s e w i d t h m e a s u r e m e n t m o d e c n t r 0 a c t i v e e d g e s w i t c h b i t 0 : c o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e s t a r t f r o m h o u t p u t i n p u l s e o u t p u t m o d e m e a s u r e h p u l s e w i d t h i n p u l s e w i d t h m e a s u r e m e n t m o d e f a l l i n g e d g e a c t i v e f o r c n t r 0 i n t e r r u p t 1 : c o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e s t a r t f r o m l o u t p u t i n p u l s e o u t p u t m o d e m e a s u r e l p u l s e w i d t h i n p u l s e w i d t h m e a s u r e m e n t m o d e r i s i n g e d g e a c t i v e f o r c n t r 0 i n t e r r u p t t i m e r x s t o p c o n t r o l b i t 0 : c o u n t s t a r t 1 : c o u n t s t o p b 7 b 0
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 26 timer y timer y is a 16-bit timer that can be selected in one of four modes. (1) timer mode the timer counts f(x in )/16 (or f(x cin )/16 in low-speed mode). (2) period measurement mode cntr 1 interrupt request is generated at rising/falling edge of cntr 1 pin input signal. simultaneously, the value in timer y latch is reloaded in timer y and timer y continues counting down. ex- cept for the above-mentioned, the operation in period measure- ment mode is the same as in timer mode. the timer value just before the reloading at rising/falling of cntr 1 pin input signal is retained until the timer y is read once after the reload. the rising/falling timing of cntr 1 pin input signal is found by cntr 1 interrupt. when using a timer in this mode, set the corre- sponding port p5 5 direction register to input mode. (3) event counter mode the timer counts signals input through the cntr 1 pin. except for this, the operation in event counter mode is the same as in timer mode. when using a timer in this mode, set the corre- sponding port p5 5 direction register to input mode. (4) pulse width hl continuously measure- ment mode cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal. except for this, the operation in pulse width hl continuously measurement mode is the same as in period measurement mode. when using a timer in this mode, set the corresponding port p5 5 direction register to input mode. note on cntr 1 interrupt active edge selection cntr 1 interrupt active edge depends on the cntr 1 active edge switch bit. however, in pulse width hl continuously measurement mode, cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal regardless of the setting of cntr 1 active edge switch bit. fig. 21 structure of timer y mode register t i m e r y m o d e r e g i s t e r ( t y m : a d d r e s s 0 0 2 8 1 6 ) b 7 b 0 not used (return 0 when read) timer y operating mode bits b5 b4 0 0 : timer mode 0 1 : period measurement mode 1 0 : event counter mode 1 1 : pulse width hl continuously measurement mode cntr 1 active edge switch bit 0 : count at rising edge in event counter mode measure the falling edge to falling edge period in period measurement mode falling edge active for cntr 1 interrupt 1 : count at falling edge in event counter mode measure the rising edge period in period measurement mode rising edge active for cntr 1 interrupt timer y stop control bit 0 : count start 1 : count stop
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 27 timer 1, timer 2, timer 3 timer 1, timer 2, and timer 3 are 8-bit timers. the count source for each timer can be selected by timer 123 mode register. the timer latch value is not affected by a change of the count source. how- ever, because changing the count source may cause an inadvert- ent count down of the timer. therefore, rewrite the value of timer whenever the count source is changed. timer 2 write control if the timer 2 write control bit is 0 , when the value is written in the address of timer 2, the value is loaded in the timer 2 and the latch at the same time. if the timer 2 write control bit is 1 , when the value is written in the address of timer 2, the value is loaded only in the latch. the value in the latch is loaded in timer 2 after timer 2 underflows. timer 2 output control when the timer 2 (t out ) is output enabled, an inversion signal from pin t out is output each time timer 2 underflows. in this case, set the port p5 6 shared with the port t out to the out- put mode. note on timer 1 to timer 3 when the count source of timers 1 to 3 is changed, the timer counting value may be changed large because a thin pulse is gen- erated in count input of timer. if timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may be changed large be- cause a thin pulse is generated in timer 1 output. therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3. fig. 22 structure of timer 123 mode register t o u t o u t p u t a c t i v e e d g e s w i t c h b i t 0 : s t a r t a t h o u t p u t 1 : s t a r t a t l o u t p u t t o u t / o u t p u t c o n t r o l b i t 0 : t o u t / o u t p u t d i s a b l e d 1 : t o u t / o u t p u t e n a b l e d t i m e r 2 w r i t e c o n t r o l b i t 0 : w r i t e d a t a i n l a t c h a n d c o u n t e r 1 : w r i t e d a t a i n l a t c h o n l y t i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t 0 : t i m e r 1 o u t p u t 1 : f ( x i n ) / 1 6 ( o r f ( x c i n ) / 1 6 i n l o w - s p e e d m o d e ) t i m e r 3 c o u n t s o u r c e s e l e c t i o n b i t 0 : t i m e r 1 o u t p u t 1 : f ( x i n ) / 1 6 ( o r f ( x c i n ) / 1 6 i n l o w - s p e e d m o d e ) t i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t 0 : f ( x i n ) / 1 6 ( o r f ( x c i n ) / 1 6 i n l o w - s p e e d m o d e ) 1 : f ( x c i n ) n o t u s e d ( r e t u r n 0 w h e n r e a d ) t i m e r 1 2 3 m o d e r e g i s t e r ( t 1 2 3 m : a d d r e s s 0 0 2 9 1 6 ) n ote: i nterna l c l oc k i s f(x cin ) /2 i n t h e l ow-spee d mo d e. b 7 b 0
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 28 serial i/o serial i/o1 serial i/o1 can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer (baud rate generator) is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o mode can be selected by setting the mode selection bit of the serial i/o1 control register to 1 . for clock synchronous serial i/o1, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the tb/rb (address 0018 16 ). fig. 23 block diagram of clock synchronous serial i/o1 fig. 24 operation of clock synchronous serial i/o1 function p 4 6 / s c l k 1 p 4 7 / s rdy1 p 4 4 / r x d p 4 5 / t x d x i n 1/4 1 / 4 f / f serial i/o1 status register s e r i a l i / o 1 c o n t r o l r e g i s t e r receive buffer register add ress 0018 16 r e c e i v e s h i f t r e g i s t e r r ece i ve b u ff er f u ll fl ag (rbf) r e c e i v e i n t e r r u p t r e q u e s t ( r i ) clock control circuit s h i f t c l o c k s e r i a l i / o 1 s y n c h r o n i z a t i o n c l o c k s e l e c t i o n b i t f r e q u e n c y d i v i s i o n r a t i o 1 / ( n + 1 ) baud rate generator a d d r e s s 0 0 1 c 1 6 brg count source se l ect i on bi t c l o c k c o n t r o l c i r c u i t falling-edge detector d a t a b u s a d d r e s s 0 0 1 8 1 6 shif t c l oc k t ransm i t s hif t reg i ster s hif t comp l et i on fl ag (tsc) t ransm i t b u ff er empty fl ag (tbe) t r a n s m i t i n t e r r u p t r e q u e s t ( t i ) t ransm i t i nterrupt source se l ect i on bi t add ress 0019 16 d a t a b u s a d d r e s s 0 0 1 a 1 6 transmit buffer register (tb) transmit shift register r e c e i v e e n a b l e s i g n a l s r d y 1 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 tbe = 0 t b e = 1 t s c = 0 t rans f er s hif t c l oc k (1/2 to 1/2048 of the internal clock, or an external clock) s e r i a l o u t p u t t x d s e r i a l i n p u t r x d w r i te s i gna l to rece i ve/transm i t buffer register (address 0018 16 ) o v e r r u n e r r o r ( o e ) d e t e c t i o n n o t e s 1 : t h e t r a n s m i t i n t e r r u p t ( t i ) c a n b e g e n e r a t e d e i t h e r w h e n t h e t r a n s m i t b u f f e r r e g i s t e r h a s e m p t i e d ( t b e = 1 ) o r a f t e r t h e t r a n s m i t s h i f t o p e r a t i o n h a s e n d e d ( t s c = 1 ) , b y s e t t i n g t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) o f t h e s e r i a l i / o 1 c o n t r o l r e g i s t e r . 2 : i f d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n t s c = 0 , t h e t r a n s m i t c l o c k i s g e n e r a t e d c o n t i n u o u s l y a n d s e r i a l d a t a i s o u t p u t c o n t i n u o u s l y f r o m t h e t x d p i n . 3 : t h e r e c e i v e i n t e r r u p t ( r i ) i s s e t w h e n t h e r e c e i v e b u f f e r f u l l f l a g ( r b f ) b e c o m e s 1 . d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 29 (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o mode selection bit of the serial i/o1 control register to 0 . eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer regis- ter, but the two buffers have the same address in memory. since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. the transmit buffer can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. fig. 25 block diagram of uart serial i/o1 fig. 26 operation of uart serial i/o1 function x in 1/4 o e p e f e 1 / 1 6 1/16 d a t a b u s r e c e i v e b u f f e r r e g i s t e r a d d r e s s 0 0 1 8 1 6 r e c e i v e s h i f t r e g i s t e r r e c e i v e b u f f e r f u l l f l a g ( r b f ) r e c e i v e i n t e r r u p t r e q u e s t ( r i ) b au d rate generator f requency di v i s i on rat i o 1/ ( n+1 ) add ress 001 c 16 st/sp/pa generator transmit buffer register d ata b us t r a n s m i t s h i f t r e g i s t e r a d d r e s s 0 0 1 8 1 6 t r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g ( t s c ) t ransm i t b u ff er empty fl ag (tbe) t ransm i t i nterrupt request (ti) a d d r e s s 0 0 1 9 1 6 s t d e t e c t o r sp d etector uart contro l reg i ster add ress 001 b 16 ch aracter l engt h se l ect i on bi t a d d r e s s 0 0 1 a 1 6 b r g c o u n t s o u r c e s e l e c t i o n b i t t ransm i t i nterrupt source se l ect i on bit s e r i a l i / o 1 s y n c h r o n i z a t i o n c l o c k s e l e c t i o n b i t c l o c k c o n t r o l c i r c u i t c h a r a c t e r l e n g t h s e l e c t i o n b i t 7 b i t s 8 bits s er i a l i / o 1 contro l reg i ster p 4 6 / s c l k 1 s e r i a l i / o 1 s t a t u s r e g i s t e r p 4 4 / r x d p 4 5 / t x d tsc =0 tbe=1 r b f = 0 t b e = 0 t b e = 0 rbf =1 r b f = 1 s t d 0 d 1 sp d 0 d 1 s t s p tbe =1 t s c = 1 ? s t d 0 d 1 sp d 0 d 1 st s p t r a n s m i t b u f f e r w r i t e s i g n a l ? g e n e r a t e d a t 2 n d b i t i n 2 - s t o p - b i t m o d e 1 start bi t 7 or 8 data bits 1 or 0 parity bit 1 or 2 stop bit (s) 1 : e r r o r f l a g d e t e c t i o n o c c u r s a t t h e s a m e t i m e t h a t t h e r b f f l a g b e c o m e s 1 ( a t 1 s t s t o p b i t , d u r i n g r e c e p t i o n ) . 2 : t h e t r a n s m i t i n t e r r u p t ( t i ) c a n b e g e n e r a t e d t o o c c u r w h e n e i t h e r t h e t b e o r t s c f l a g b e c o m e s 1 , d e p e n d i n g o n t h e s e t t i n g o f t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) o f t h e s e r i a l i / o 1 c o n t r o l r e g i s t e r . 3 : t h e r e c e i v e i n t e r r u p t ( r i ) i s s e t w h e n t h e r b f f l a g b e c o m e s 1 . n o t e s s e r i a l o u t p u t t x d s e r i a l i n p u t r x d r e c e i v e b u f f e r r e a d s i g n a l t r a n s m i t o r r e c e i v e c l o c k
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 30 [transmit buffer/receive buffer register (tb/ rb)] 0018 16 the transmit buffer register and the receive buffer register are lo- cated at the same address. the transmit buffer register is write- only and the receive buffer register is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer regis- ter is 0 . [serial i/o1 status register (sio1sts)] 0019 16 the read-only serial i/o1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o1 function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to 0 when the receive buffer is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. a write to the serial i/o1 status register clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing 0 to the serial i/o1 enable bit sioe (bit 7 of the serial i/o1 control register) also clears all the status flags, including the error flags. all bits of the serial i/o1 status register are initialized to 0 at re- set, but if the transmit enable bit (bit 4) of the serial i/o1 control register has been set to 1 , the transmit shift register shift comple- tion flag (bit 2) and the transmit buffer empty flag (bit 0) become 1 . [serial i/o1 control register (sio1con)] 001a 16 the serial i/o1 control register contains eight control bits for the serial i/o1 function. [uart control register (uartcon)] 001b 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer. one bit in this register (bit 4) is always valid and sets the output structure of the p4 5 /t x d pin. [baud rate generator (brg)] 001c 16 the baud rate generator determines the baud rate for serial trans- fer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor. notes on serial i/o when setting the transmit enable bit to 1 , the serial i/o1 transmit interrupt request bit is automatically set to 1 . when not requiring the interrupt occurrence synchronous with the transmission enalbed, take the following sequence. ? set the serial i/o1 transmit interrupt enable bit to 0 (disabled). ? set the transmit enable bit to 1 . ? set the serial i/o1 transmit interrupt request bit to 0 after 1 or more instructions have been executed. ? set the serial i/o1 transmit interrupt enable bit to 1 (enabled).
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 31 fig. 27 structure of serial i/o1 control registers b r g c o u n t s o u r c e s e l e c t i o n b i t ( c s s ) 0 : f ( x i n ) 1 : f ( x i n ) / 4 s e r i a l i / o 1 s y n c h r o n i z a t i o n c l o c k s e l e c t i o n b i t ( s c s ) 0 : b r g o u t p u t d i v i d e d b y 4 w h e n c l o c k s y n c h r o n o u s s e r i a l i / o i s s e l e c t e d . b r g o u t p u t d i v i d e d b y 1 6 w h e n u a r t i s s e l e c t e d . 1 : e x t e r n a l c l o c k i n p u t w h e n c l o c k s y n c h r o n o u s s e r i a l i / o i s s e l e c t e d . e x t e r n a l c l o c k i n p u t d i v i d e d b y 1 6 w h e n u a r t i s s e l e c t e d . s r d y 1 o u t p u t e n a b l e b i t ( s r d y ) 0 : p 4 7 p i n o p e r a t e s a s o r d i n a r y i / o p i n 1 : p 4 7 p i n o p e r a t e s a s s r d y 1 o u t p u t p i n t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) 0 : i n t e r r u p t w h e n t r a n s m i t b u f f e r h a s e m p t i e d 1 : i n t e r r u p t w h e n t r a n s m i t s h i f t o p e r a t i o n i s c o m p l e t e d t r a n s m i t e n a b l e b i t ( t e ) 0 : t r a n s m i t d i s a b l e d 1 : t r a n s m i t e n a b l e d r e c e i v e e n a b l e b i t ( r e ) 0 : r e c e i v e d i s a b l e d 1 : r e c e i v e e n a b l e d s e r i a l i / o 1 m o d e s e l e c t i o n b i t ( s i o m ) 0 : a s y n c h r o n o u s s e r i a l i / o ( u a r t ) 1 : c l o c k s y n c h r o n o u s s e r i a l i / o s e r i a l i / o 1 e n a b l e b i t ( s i o e ) 0 : s e r i a l i / o 1 d i s a b l e d ( p i n s p 4 4 p 4 7 o p e r a t e a s o r d i n a r y i / o p i n s ) 1 : s e r i a l i / o 1 e n a b l e d ( p i n s p 4 4 p 4 7 o p e r a t e a s s e r i a l i / o p i n s ) s er i a l i / o 1 contro l reg i ster (sio1con : address 001a 16 ) b 7b 0 t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) 0 : b u f f e r f u l l 1 : b u f f e r e m p t y r e c e i v e b u f f e r f u l l f l a g ( r b f ) 0 : b u f f e r e m p t y 1 : b u f f e r f u l l t r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g ( t s c ) 0 : t r a n s m i t s h i f t i n p r o g r e s s 1 : t r a n s m i t s h i f t c o m p l e t e d o v e r r u n e r r o r f l a g ( o e ) 0 : n o e r r o r 1 : o v e r r u n e r r o r p a r i t y e r r o r f l a g ( p e ) 0 : n o e r r o r 1 : p a r i t y e r r o r f r a m i n g e r r o r f l a g ( f e ) 0 : n o e r r o r 1 : f r a m i n g e r r o r s u m m i n g e r r o r f l a g ( s e ) 0 : ( o e ) u ( p e ) u ( f e ) = 0 1 : ( o e ) u ( p e ) u ( f e ) = 1 n o t u s e d ( r e t u r n s 1 w h e n r e a d ) s e r i a l i / o 1 s t a t u s r e g i s t e r ( s i o 1 s t s : a d d r e s s 0 0 1 9 1 6 ) b 7b 0 u a r t c o n t r o l r e g i s t e r ( u a r t c o n : a d d r e s s 0 0 1 b 1 6 ) c h a r a c t e r l e n g t h s e l e c t i o n b i t ( c h a s ) 0 : 8 b i t s 1 : 7 b i t s p a r i t y e n a b l e b i t ( p a r e ) 0 : p a r i t y c h e c k i n g d i s a b l e d 1 : p a r i t y c h e c k i n g e n a b l e d p a r i t y s e l e c t i o n b i t ( p a r s ) 0 : e v e n p a r i t y 1 : o d d p a r i t y s t o p b i t l e n g t h s e l e c t i o n b i t ( s t p s ) 0 : 1 s t o p b i t 1 : 2 s t o p b i t s p 4 5 / t x d p - c h a n n e l o u t p u t d i s a b l e b i t ( p o f f ) 0 : c m o s o u t p u t ( i n o u t p u t m o d e ) 1 : n - c h a n n e l o p e n - d r a i n o u t p u t ( i n o u t p u t m o d e ) n o t u s e d ( r e t u r n 1 w h e n r e a d ) b 7b 0
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 32 serial i/o2 the serial i/o2 function can be used only for clock synchronous serial i/o. for clock synchronous serial i/o2, the transmitter and the receiver must use the same clock. when the internal clock is used, transfer is started by a write signal to the serial i/o2 register. when an internal clock is selected as the synchronous clock of the serial i/o2, either p6 2 or p6 3 can be selected as an output pin of the synchronous clock. in this case, the pin that is not selected as an output pin of the synchronous clock functions as a port. [serial i/o2 control register (sio2con)] 001d16 the serial i/o2 control register contains 8 bits which control vari- ous serial i/o2 functions. fig. 28 structure of serial i/o2 control register fig. 29 block diagram of serial i/o2 function serial i/o2 control register (sio2con : address 001d 16 ) b7 internal synchronous clock select bits 0 0 0: f(x in )/8 0 0 1: f(x in )/16 0 1 0: f(x in )/32 0 1 1: f(x in )/64 1 0 0: 1 0 1: 1 1 0: f(x in )/128 1 1 1: f(x in )/256 serial i/o2 port selection bit 0: i/o port 1: s out2 ,s clk21 /s clk22 signal output p6 1 /s out2 p-channel output disable bit 0: cmos output (in output mode) 1: n-channel open-drain output (in output mode) transfer direction selection bit 0: lsb first 1: msb first synchronous clock selection bit 0: external clock 1: internal clock synchronous clock output pin selection bit 0: s clk21 1: s clk22 b0 b2 b1 b0 do not set x in 1 0 0 1 0 1 s clk2 (note) 1/8 1/16 1/32 1/64 1/128 1/256 data bus serial i/o2 interrupt request serial i/o2 port selection bit serial i/o counter 2 (3) serial i/o shift register 2 (8) synchronous circuit synchronous clock selection bit external clock internal synchronous clock select bits divider p6 3 latch p6 3 /s clk22 p6 2 /s clk21 p6 1 /s out2 p6 0 /s in2 p6 2 latch p6 1 latch (note) note: it is selected by the synchronous clock selection bit, the synchronous clock output pin selection bit, and the serial i/o port selection bit.
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 33 fig. 30 timing of serial i/o2 function d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 transfer clock (note 1) serial i/o2 output s out2 serial i/o2 input s in2 serial i/o2 register write signal (note 2) serial i/o2 interrupt request bit set 1: when the internal clock is selected as the transfer clock, the divide ratio can be selected by setting bits 0 to 2 of the seria l i/o2 control register. 2: when the internal clock is selected as the transfer clock, the s out2 pin goes to high impedance after transfer completion. when the external clock is selected as the transfer clock, a content of the serial i/o shift register is continued to shift during inputting a transfer clock. the s out2 pin does not go to high impedance after transfer completion. notes
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 34 pulse width modulation (pwm) the 7560 group has a pwm function with an 8-bit resolution, based on a signal that is the clock input x in or that clock input di- vided by 2. data setting the pwm output pin also functions as ports p5 0 and p5 1 . set the pwm period by the pwm prescaler, and set the period during which the output pulse is an h by the pwm register. if pwm count source is f(x in ) and the value in the pwm prescaler is n and the value in the pwm register is m (where n = 0 to 255 and m = 0 to 255) : pwm period = 255 ? (n+1)/f(x in ) = 31.875 ? (n+1) s (when f(x in ) = 8 mhz) output pulse h period = pwm period ? m/255 = 0.125 ? (n+1) ? m s (when f(x in ) = 8 mhz) pwm operation when at least either bit 1 (pwm 0 function enable bit) or bit 2 (pwm 1 function enable bit) of the pwm control register is set to 1 , operation starts by initializing the pwm output circuit, and pulses are output starting at an h . when one pwm output is en- abled and that the other pwm output is enabled, pwm output which is enabled to output later starts pulse output from halfway. when the pwm register or pwm prescaler is updated during pwm output, the pulses will change in the cycle after the one in which the change was made. fig. 31 timing of pwm cycle fig. 32 block diagram of pwm function 31.875 ? m ? (n+1) 255 s t = [31.875 ? (n+1)] s pwm output m: contents of pwm register n : contents of pwm prescaler t : pwm cycle (when f(x in ) = 8 mhz) d ata b us c o u n t s o u r c e s e l e c t i o n b i t 0 1 p w m p r e s c a l e r p r e - l a t c h pwm register pre-latch p w m p r e s c a l e r l a t c h p w m r e g i s t e r l a t c h t rans f er contro l c i rcu i t pwm c i rcu i t 1 / 2 x in pwm 0 f unct i on enable bit p o r t p 5 1 p w m p r e s c a l e r pwm 1 f unct i on enable bit p ort p 5 0 p o r t p 5 1 l a c t h p ort p 5 0 lacth
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 35 fig. 34 pwm output timing when pwm register or pwm prescaler is changed fig. 33 structure of pwm control register b7 b0 pwm control register (pwmcon : address 002b 16 ) count source selection bit 0 : f(x in ) 1 : f(x in )/2 pwm 0 function enable bit 0 : pwm 0 disabled 1 : pwm 0 enabled pwm 1 function enable bit 0 : pwm 1 disabled 1 : pwm 1 enabled not used (return 0 when read) t t2 c b t pwm register write signal pwm prescaler write signal (changes from a to b during h period) (changes from t to t2 during pwm period) pwm (internal) a b t c t2 = stop pwm 0 function enable bit pwm 1 function enable bit pwm 0 output port port pwm 1 output port stop port when the contents of the pwm register or pwm prescaler have changed, the pwm output will change from the next period after the change.
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 36 a-d converter the functional blocks of the a-d converter are described below. [a-d conversion register (ad)] 0035 16 the a-d conversion register is a read-only register that contains the result of an a-d conversion. when reading this register during an a-d conversion, the previous conversion result is read. [a-d control register (adcon)] 0034 16 the a-d control register controls the a-d conversion process. bits 0 to 2 of this register select specific analog input pins. bit 3 signals the completion of an a-d conversion. the value of this bit remains at 0 during an a-d conversion, then changes to 1 when the a- d conversion is completed. writing 0 to this bit starts the a-d conversion. bit 4 controls the transistor which breaks the through current of the resistor ladder. when bit 5, which is the ad external trigger valid bit, is set to 1 , this bit enables a-d conversion even by a falling edge of an adt input. set ports which share with adt pins to input when using an a-d external trigger. comparison voltage generator the comparison voltage generator divides the voltage between av ss and v ref by 256, and outputs the divided voltages. channel selector the channel selector selects one of the input ports p6 7 /an 7 p6 0 / an 0 . comparator and control circuit the comparator and control circuit compare an analog input volt- age with the comparison voltage and store the result in the a-d conversion register. when an a-d conversion is completed, the control circuit sets the ad conversion completion bit and the ad interrupt request bit to 1 . note that the comparator is constructed linked to a capacitor, so set f(x in ) to at least 500khz during a-d conversion. use the clock divided from the main clock x in as the internal clock . fig. 36 a-d converter block diagram fig. 35 structure of a-d control register a - d c o n t r o l r e g i s t e r ( a d c o n : a d d r e s s 0 0 3 4 1 6 ) a d c o n v e r s i o n c o m p l e t i o n b i t 0 : c o n v e r s i o n i n p r o g r e s s 1 : c o n v e r s i o n c o m p l e t e d a n a l o g i n p u t p i n s e l e c t i o n b i t s 0 0 0 : p 6 0 / a n 0 0 0 1 : p 6 1 / a n 1 0 1 0 : p 6 2 / a n 2 0 1 1 : p 6 3 / a n 3 1 0 0 : p 6 4 / a n 4 1 0 1 : p 6 5 / a n 5 1 1 0 : p 6 6 / a n 6 1 1 1 : p 6 7 / a n 7 v ref i nput sw i tc h bi t 0 : off 1 : on a d e x t e r n a l t r i g g e r v a l i d b i t 0 : a - d e x t e r n a l t r i g g e r i n v a l i d 1 : a - d e x t e r n a l t r i g g e r v a l i d b 7 b 0 i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : i n t e r r u p t r e q u e s t a t a - d c o n v e r s i o n c o m p l e t e d 1 : i n t e r r u p t r e q u e s t a t a d t i n p u t f a l l i n g n o t u s e d ( r e t u r n s 0 w h e n r e a d ) c o m p a r a t o r a - d contro l c i rcu it adt / a - d i nterrupt request a v s s v ref p 6 0 / s i n 2 / a n 0 d a t a b u s a - d c o n t r o l r e g i s t e r b 7 b 0 a - d convers i on register r es i stor l a dd e r c h a n n e l s e l e c t o r p 6 7 / a n 7 p 6 6 / a n 6 p 6 5 / a n 5 p 6 4 / a n 4 p 6 3 / s clk22 / an 3 p 6 2 / s clk21 / an 2 p 6 1 / s o u t2 / a n 1 p 5 7 / a d t / d a 2 8 3
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 37 d-a converter the 7560 group has an on-chip d-a converter with 8-bit resolution and 2 channels (dai (i=1, 2)). after the da 1 selection bit or da 2 selection bit is set to 0 , the d-a converter is performed by setting the value in the d-a conversion register. the result of d-a con- verter is output from dai pin. when using the d-a converter, the corresponding port direction register bit (p5 6 /da 1 , p5 7 /da 2 ) should be set to 0 (input status) and the pull-up resistor should be in the off state. the output analog voltage v is determined by the value n (base 10) in the d-a conversion register as follows: v=v ref ? n/256 (n=0 to 255) where v ref is the reference voltage. at reset, the d-a conversion registers are cleared to 00 16 , the dai output enable bits are cleared to 0 , and dai pin goes to high impedance state. the da output is not buffered, so connect an external buffer when driving a low-impedance load. note on applied voltage to v ref pin when the p5 6 /da 1 pin and p5 7 /da 2 pin are used as i/o ports, be sure to apply vcc level to v ref pin. when these pins are used as d-a conversion output pins, the vcc level is recommended for the applied voltage to v ref pin. when the voltage below vcc level is applied, the d-a conversion accuracy may be worse. fig. 37 structure of d-a control register fig. 38 block diagram of d-a converter da 1 output enable bit 0 : disabled 1 : enabled da 2 output enable bit 0 : disabled 1 : enabled not used (return 0 when read) (do not write 1 to these bits.) b7 b0 d-a control register (dacon : address 0036 16 ) d - a 1 c o n v e r s i o n r e g i s t e r ( d a 1 : a d d r e s s 0 0 3 2 1 6 ) d - a 2 c o n v e r s i o n r e g i s t e r ( d a 2 : a d d r e s s 0 0 3 3 1 6 ) p5 6 /da 1 p5 7 /da 2 data bus d-a i conversion register (8) r-2r resistor ladder d a i o u t p u t e n a b l e b i t
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 38 lcd drive control circuit the 7560 group has the built-in liquid crystal display (lcd) drive control circuit consisting of the following. lcd display ram segment output enable register lcd mode register voltage multiplier selector timing controller common driver segment driver bias control circuit a maximum of 40 segment output pins and 4 common output pins can be used. up to 160 pixels can be controlled for lcd display. when the lcd fig. 39 structure of segment output enable register and lcd mode register enable bit is set to 1 after data is set in the lcd mode register, the segment output enable register and the lcd display ram, the lcd drive control circuit starts reading the display data automati- cally, performs the bias control and the duty ratio control, and dis- plays the data on the lcd panel. table 9. maximum number of display pixels at each duty ratio duty ratio maximum number of display pixel 80 dots or 8 segment lcd 10 digits 120 dots or 8 segment lcd 15 digits 160 dots or 8 segment lcd 20 digits 2 3 4 s e g m e n t o u t p u t e n a b l e b i t 0 0 : o u t p u t p o r t s p 3 0 p 3 5 1 : s e g m e n t o u t p u t s e g 1 8 s e g 2 3 s e g m e n t o u t p u t e n a b l e b i t 1 0 : o u t p u t p o r t s p 3 6 , p 3 7 1 : s e g m e n t o u t p u t s e g 2 4 , s e g 2 5 s e g m e n t o u t p u t e n a b l e b i t 2 0 : i / o p o r t s p 0 0 p 0 5 1 : s e g m e n t o u t p u t s e g 2 6 s e g 3 1 s e g m e n t o u t p u t e n a b l e b i t 3 0 : i / o p o r t s p 0 6 , p 0 7 1 : s e g m e n t o u t p u t s e g 3 2 , s e g 3 3 s e g m e n t o u t p u t e n a b l e b i t 4 0 : i / o p o r t p 1 0 1 : s e g m e n t o u t p u t s e g 3 4 s e g m e n t o u t p u t e n a b l e b i t 5 0 : i / o p o r t s p 1 1 p 1 5 1 : s e g m e n t o u t p u t s e g 3 5 s e g 3 9 l c d o u t p u t e n a b l e b i t 0 : d i s a b l e d 1 : e n a b l e d n o t u s e d ( r e t u r n 0 w h e n r e a d ) ( d o n o t w r i t e 1 t o t h i s b i t ) s egment output ena bl e reg i ster (seg : address 0038 16 ) b 7 b 0 l c d m o d e r e g i s t e r ( l m : a d d r e s s 0 0 3 9 1 6 ) d u t y r a t i o s e l e c t i o n b i t s 0 0 : n o t u s e d 0 1 : 2 d u t y ( u s e c o m 0 , c o m 1 ) 1 0 : 3 d u t y ( u s e c o m 0 c o m 2 ) 1 1 : 4 d u t y ( u s e c o m 0 c o m 3 ) b i a s c o n t r o l b i t 0 : 1 / 3 b i a s 1 : 1 / 2 b i a s l c d e n a b l e b i t 0 : l c d o f f 1 : l c d o n v o l t a g e m u l t i p l i e r c o n t r o l b i t 0 : v o l t a g e m u l t i p l i e r d i s a b l e 1 : v o l t a g e m u l t i p l i e r e n a b l e l c d c i r c u i t d i v i d e r d i v i s i o n r a t i o s e l e c t i o n b i t s 0 0 : c l o c k i n p u t 0 1 : 2 d i v i s i o n o f c l o c k i n p u t 1 0 : 4 d i v i s i o n o f c l o c k i n p u t 1 1 : 8 d i v i s i o n o f c l o c k i n p u t l c d c k c o u n t s o u r c e s e l e c t i o n b i t ( n o t e ) 0 : f ( x c i n ) / 3 2 1 : f ( x i n ) / 8 1 9 2 ( f ( x c i n ) / 8 1 9 2 i n l o w - s p e e d m o d e ) n o t e : l c d c k i s a c l o c k f o r a l c d t i m i n g c o n t r o l l e r . b 7 b 0
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 39 fig. 40 block diagram of lcd controller/driver d a t a b u s t i m i n g c o n t r o l l e r l c d d i v i d e r f ( x i n ) / 8 1 9 2 ( f ( x c i n ) / 8 1 9 2 i n l o w - s p e e d m o d e ) f ( x c i n ) / 3 2 c o m 0 c o m 1 c o m 2 c o m 3 v s s v l 1 v l 2 v l 3 s e g 3 s e g 2 s e g 1 s e g 0 a d d r e s s 0 0 4 0 1 6 a d d r e s s 0 0 4 1 1 6 1 0 l c d c k l c d c k c o u n t s o u r c e s e l e c t i o n b i t l c d c i r c u i t d i v i d e r d i v i s i o n r a t i o s e l e c t i o n b i t s b i a s c o n t r o l b i t l c d e n a b l e b i t d u t y r a t i o s e l e c t i o n b i t s 2 2 s e l e c t o rs e l e c t o rs e l e c t o r s e l e c t o r s e l e c t o r s e l e c t o r l c d d i s p l a y r a m a d d r e s s 0 0 5 3 1 6 p 1 4 / s e g 3 8 p 3 0 / s e g 1 8 p 1 5 / s e g 3 9 l e v e l s h i f t l e v e l s h i f t l e v e l s h i f t l e v e l s h i f t l e v e l s h i f t l e v e l s h i f t c o m m o n d r i v e r c o m m o n d r i v e r c o m m o n d r i v e r c o m m o n d r i v e r c 1 c 2 v o l t a g e m u l t i p l i e r c o n t r o l b i t l e v e l s h i f t l e v e l s h i f t l e v e l s h i f t l e v e l s h i f t s e g m e n t d r i v e r s e g m e n t d r i v e r s e g m e n t d r i v e r s e g m e n t d r i v e r s e g m e n t d r i v e r s e g m e n t d r i v e r b i a s c o n t r o l l c d o u t p u t e n a b l e b i t v c c
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 40 voltage multiplier (3 times) the voltage multiplier performs threefold boosting. this circuit in- puts a reference voltage for boosting from lcd power input pin v l1 . (however, when using a 1/2 bias, connect v l1 and v l2 and apply voltage by external resistor division.) set each bit of the segment output enable register and the lcd mode register in the following order for operating the voltage mul- tiplier. 1. set the segment output enable bits (bits 0 to 5) of the seg- ment output enable register to 0 or 1. 2. set the duty ratio selection bits (bits 0 and 1), the bias con- trol bit (bit 2), the lcd circuit divider division ratio selection bits (bits 5 and 6), and the lcdck count source selection bit (bit 7) of the lcd mode register to 0 or 1. 3. set the lcd output enable bit (bit 6) of the segment output enable register to 1. 4. set the voltage multiplier control bit (bit 4) of the lcd mode register to 1. when voltage is input to the v l1 pin during operating the voltage multiplier, voltage that is twice as large as v l1 occurs at the v l2 pin, and voltage that is three times as large as v l1 occurs at the v l3 pin. when using the voltage multiplier, apply 1.3 v voltage 2.1 v to the v l1 pin. when not using the voltage multiplier,apply proper voltage to the lcd power input pins (v l1 v l3 ). then set the lcd output enable bit to 1. when the lcd output enable bit is set to 0, the v cc voltage is applied to the v l3 pin inside of this microcomputer. the voltage multiplier control bit (bit 4 of the lcd mode register) controls the voltage multiplier. fig. 41 example of circuit at each bias table 10. bias control and applied voltage to v l1 ? l3 bias value 1/3 bias 1/2 bias voltage value v l3 =v lcd v l2 =2/3 v lcd v l1 =1/3 v lcd v l3 =v lcd v l2 =v l1 =1/2 v lcd note : v lcd is the maximum value of supplied voltage for the lcd panel. v l 3 v l 2 c 2 c 1 v l 1 1 / 3 b i a s w h e n u s i n g t h e v o l t a g e m u l t i p l i e r v l 3 v l 2 c 2 c 1 v l 1 1 / 3 b i a s w h e n n o t u s i n g t h e v o l t a g e m u l t i p l i e r o p e n o p e n r 2 r 1 r 3 r 1 = r 2 = r 3 c o n t r a s t c o n t r o l v l 3 v l 2 c 2 c 1 v l 1 1 / 2 b i a s o p e n o p e n r 4 r 5 r 4= r 5 c o n t r a s t c o n t r o l px x bias control and applied voltage to lcd power input pins to the lcd power input pins (v l1 v l3 ), apply the voltage shown in table 10 according to the bias value. select a bias value by the bias control bit (bit 2 of the lcd mode register).
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 41 (frequency of count source for lcdck) (divider division ratio for lcd) f(lcdck)= f(lcdck) duty ratio frame frequency= fig. 42 lcd display ram map common pin and duty ratio control the common pins (com 0 com 3 ) to be used are determined by duty ratio. select duty ratio by the duty ratio selection bits (bits 0 and 1 of the lcd mode register). when releasing from reset, the v cc (v l3 ) voltage is output from the common pins. lcd display ram address 0040 16 to 0053 16 is the designated ram for the lcd dis- play. when 1 are written to these addresses, the corresponding segments of the lcd display panel are turned on. lcd drive timing the lcdck timing frequency (lcd drive timing) is generated in- ternally and the frame frequency can be determined with the fol- lowing equation; table 11. duty ratio control and common pins used duty ratio 2 3 4 common pins used notes 1: com 2 and com 3 are open. 2: com 3 is open. bit 1 0 1 1 bit 0 1 0 1 com 0 , com 1 (note 1) com 0 com 2 (note 2) com 0 com 3 duty ratio selection bits segment signal output pin segment signal output pins are classified into the segment-only pins (seg 0 seg 17 ), the segment/output port pins (seg 18 seg 25 ), and the segment/i/o port pins (seg 26 seg 39 ). segment signals are output according to the bit data of the lcd ram corresponding to the duty ratio. after reset release, a v cc (=v l3 ) voltage is output to the segment-only pins and the seg- ment/output port pins are the high impedance condition and pulled up to v cc (=v l3 ) voltage. also, the segment/i/o port pins(seg 26 seg 39 ) are set to input ports, and v cc (=v l3 ) is applied to them by pull-up resistor. 0 0 4 0 1 6 0 0 4 1 1 6 0 0 4 2 1 6 0 0 4 3 1 6 0 0 4 4 1 6 0 0 4 5 1 6 0 0 4 6 1 6 0 0 4 7 1 6 0 0 4 8 1 6 0 0 4 9 1 6 0 0 4 a 1 6 0 0 4 b 1 6 0 0 4 c 1 6 0 0 4 d 1 6 0 0 4 e 1 6 0 0 4 f 1 6 0 0 5 0 1 6 0 0 5 1 1 6 0 0 5 2 1 6 0 0 5 3 1 6 b i t add ress s e g 1 s e g 3 s e g 5 s e g 7 s e g 9 s e g 1 1 s e g 1 3 s e g 1 5 s e g 1 7 s e g 1 9 s e g 2 1 s e g 2 3 s e g 2 5 s e g 2 7 s e g 2 9 s e g 3 1 s e g 3 3 s e g 3 5 s e g 3 7 s e g 3 9 76543210 c o m 3 c o m 0 c o m 2 c o m 1 c o m 0 c o m 3 c o m 2 c o m 1 s e g 0 s e g 2 s e g 4 s e g 6 s e g 8 s e g 1 0 s e g 1 2 s e g 1 4 s e g 1 6 s e g 1 8 s e g 2 0 s e g 2 2 s e g 2 4 s e g 2 6 s e g 2 8 s e g 3 0 s e g 3 2 s e g 3 4 s e g 3 6 s e g 3 8
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 42 fig. 43 lcd drive waveform (1/2 bias) i n t e r n a l l o g i c l c d c k t i m i n g 1 / 4 d u t y voltage level v l 3 v l 2 = v l 1 v s s v l 3 v ss c o m 0 c o m 1 c o m 2 c o m 3 s e g 0 off on off on com 3 com 2 com 1 com 0 com 3 com 2 com 1 com 0 1 / 3 d u t y v l 3 v l 2 = v l 1 v ss v l3 v ss o f f o n o noff o no f f 1 / 2 d u t y com 0 c o m 1 c o m 2 s e g 0 c o m 0 c o m 1 seg 0 v l 3 v l 2 = v l 1 v s s v l 3 v s s off on off on off on off on com 0 c o m 2 c o m 1 com 0 c o m 2 c o m 1 com 0 com 2 com 1 c o m 0 c o m 1 com 0 c o m 1 c o m 0 com 1 com 0
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 43 fig. 44 lcd drive waveform (1/3 bias) i n t e r n a l l o g i c l c d c k t i m i n g 1 / 4 d u t y v o l t a g e l e v e l v l 3 v s s c o m 0 c o m 1 c o m 2 c o m 3 s e g 0 o f fo n o f fon com 3 com 2 com 1 com 0 com 3 com 2 com 1 com 0 1/3 duty off o n o no f f on o f f 1 / 2 d u t y com 0 c o m 1 com 2 seg 0 c o m 0 com 1 s e g 0 off on off on off on off on v l 3 v l 2 v s s v l 1 v l 3 v l2 v s s v l 1 v l 3 v s s v l 3 v l 2 v ss v l 1 v l 3 v s s com 0 c o m 2 c o m 1 c o m 0 com 2 com 1 com 0 com 2 c o m 1 c o m 0 c o m 1 c o m 0 com 1 c o m 0 c o m 1 c o m 0
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 44 watchdog timer the watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software runaway). the watchdog timer consists of an 8-bit watchdog timer l and a 6- bit watchdog timer h. at reset or writing to the watchdog timer control register (address 0037 16 ), the watchdog timer is set to 3fff 16 . when any data is not written to the watchdog timer con- trol register (address 0037 16 ) after reset, the watchdog timer is in stop state. the watchdog timer starts to count down from 3fff 16 by writing an optional value into the watchdog timer control regis- ter (address 0037 16 ) and an internal reset occurs at an underflow. accordingly, programming is usually performed so that writing to the watchdog timer control register (address 0037 16 ) may be started before an underflow. the watchdog timer does not function when an optional value has not been written to the watchdog timer control register (address 0037 16 ). when address 0037 16 is read, the following values are read: value of high-order 6-bit counter value of stp instruction disable bit value of count source selection bit. when bit 6 of the watchdog timer control register (address 0037 16 ) is set to 0, the stp instruction is valid. the stp instruction is disabled by rewriting this bit to 1. at this time, if the stp instruc- tion is executed, it is processed as an undefined instruction, so that a reset occurs inside. this bit cannot be rewritten to 0 by programming. this bit is 0 immediately after reset. the count source of the watchdog timer becomes the system clock divided by 8. the detection time in this case is set to 8.19 s at f(x cin ) = 32 khz and 32.768 ms at f(x in ) = 8 mhz. however, count source of high-order 6-bit timer can be connected to a signal divided system clock by 8 directly by writing the bit 7 of the watchdog timer control register (address 0037 16 ) to 1. the detection time in this case is set to 32 ms at f(x cin ) = 32 khz and 128 s at f(x in ) = 8 mhz. there is no difference in the detection time between the middle-speed mode and the high-speed mode. fig. 45 block diagram of watchdog timer fig. 46 structure of watchdog timer control register fig. 47 timing of reset output x in data bus x cin 1 0 internal system clock selection bit (note) 0 1 1/16 watchdog timer h count source selection bit reset circuit undefined instruction reset 3f 16 is set when watchdog timer is written to. internal reset reset reset release time wait ff 16 is set when watchdog timer is written to. stp instruction stp instruction disable bit watchdog timer h (6) watchdog timer l (8) note: this is the bit 7 of cpu mode register and is used to switch the middle-/high-speed mode and low-speed mode. b 7 b 0 w a t c h d o g t i m e r r e g i s t e r ( a d d r e s s 0 0 3 7 1 6 ) w d t c o n s t p i n s t r u c t i o n d i s a b l e b i t 0 : s t p i n s t r u c t i o n e n a b l e d 1 : s t p i n s t r u c t i o n d i s a b l e d watchdog timer h count source selecion bit 0 : watchdog timer l underflow 1 : f(x in )/16 or f(x cin )/16 w a t c h d o g t i m e r h ( f o r r e a d - o u t o f h i g h - o r d e r 6 b i t ) 3 f f f 1 6 i s s e t t o t h e w a t c h d o g t i m e r b y w r i t i n g v a l u e s t o t h i s a d d r e s s . i n t e r n a l r e s e t s i g n a l w a t c h d o g t i m e r d e t e c t i o n ? 1 m s ( f ( x i n ) = 8 m h z ) f ( x i n )
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 45 tout/ clock output function the internal system clock or timer 2 divided by 2 (t out output) can be output from port p4 3 by setting the t out / output control bit (bit 1) of the timer 123 mode register and the t out / output control register. set bit 3 of the port p4 direction register to 1 when outputting the clock. fig. 48 structure of t out / output-related register t out / output control bit 0 : clock output 1 : t out output not used (return 0 when read) t out / output control register (ckout : address 002a 16 ) b7 b0 timer 123 mode register (t123m : address 0029 16 ) t out output active edge switch bit 0 : start at h output 1 : start at l output t out / output control bit 0 : t out / output disabled 1 : t out / output enabled timer 2 write control bit 0 : write data in latch and timer 1 : write data in latch only timer 2 count source selection bit 0 : timer 1 output 1 : f(x in )/16 (or f(x cin )/16 in low-speed mode ? ) timer 3 count source selection bit 0 : timer 1 output 1 : f(x in )/16 (or f(x cin )/16 in low-speed mode ? ) timer 1 count source selection bit 0 : f(x in )/16 (or f(x cin )/16 in low-speed mode ? ) 1 : f(x cin ) not used (return 0 when read) ? : internal clock is f(x cin )/2 in the low-speed mode. b7 b0
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 46 fig. 49 example of reset circuit reset circuit to reset the microcomputer, reset pin should be held at an l level for 2 s or more. then the reset pin is returned to an h level (the power source voltage should be between v cc (min.) and 5.5 v, and the quartz-crystal oscillator should be stable), reset is released. after the reset is completed, the program starts from the address contained in address fffd 16 (high-order byte) and ad- dress fffc 16 (low-order byte). make sure that the reset input voltage is less than 0.2 v cc for v cc of v cc (min.). fig. 50 reset sequence p o w e r o n p o w e r s o u r c e v o l t a g e r e s e t i n p u t v o l t a g e p o w e r s o u r c e v o l t a g e d e t e c t i o n c i r c u i t 0 . 2 v c c 0v 0v v c c r e s e t v cc r e s e t n o t e : r e s e t r e l e a s e v o l t a g e v c c = v c c ( m i n . ) ( n o t e ) a d l fffc f f f d a d h , ? ? ? ? x i n : a b o u t 8 2 0 0 c l o c k c y c l e s n otes 1 : x in an d are i n t h e re l at i ons hi p : f(x in ) = 8 f( ) 2 : a question mark (?) indicates an undefined status that depends on the previous status. r e s e t a d d r e s s f r o m v e c t o r t a b l e r e s e t i n t e r n a l r e s e t a d d r e s s d a t a s y n c
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 47 fig. 51 internal state of microcomputer immediately after reset n o t e : t h e c o n t e n t s o f a l l o t h e r r e g i s t e r s a n d r a m a r e u n d e f i n e d a f t e r r e s e t , s o t h e y m u s t b e i n i t i a l i z e d b y s o f t w a r e . ? : u n d e f i n e d r eg i ster contents add ress 0 0 0 1 1 6 0 0 0 3 1 6 0 0 0 5 1 6 0 0 0 7 1 6 0009 16 0 0 0 b 1 6 0 0 0 d 1 6 0 0 0 f 1 6 0 0 1 5 1 6 0 0 1 6 1 6 0017 16 0019 16 0 0 1 a 1 6 001 b 16 0 0 1 d 1 6 0020 16 0 0 2 1 1 6 0 0 2 2 1 6 0023 16 0024 16 0 0 2 5 1 6 0 0 2 6 1 6 0027 16 0 0 2 8 1 6 0029 16 002 a 16 0 0 2 b 1 6 0 0 3 2 1 6 0 0 3 3 1 6 0034 16 0036 16 0 0 3 7 1 6 0 0 3 8 1 6 0 0 3 9 1 6 003 a 16 003 b 16 003 c 16 003 d 16 003 e 16 0 0 3 f 1 6 (ps) (pc h ) ( p c l ) ( 10 ) ( 11 ) ( 12 ) ( 13 ) ( 14 ) ( 15 ) ( 16 ) ( 17 ) ( 18 ) ( 19 ) ( 20 ) ( 21 ) ( 22 ) ( 23 ) ( 24 ) ( 25 ) ( 26 ) ( 27 ) ( 28 ) ( 29 ) ( 30 ) ( 31 ) ( 32 ) ( 33 ) ( 34 ) ( 1 ) ( 2 ) ( 3 ) ( 4 ) ( 5 ) ( 6 ) ( 7 ) ( 8 ) ( 9 ) ( 35 ) ( 36 ) ( 37 ) ( 38 ) ( 39 ) ( 40 ) ( 41 ) ( 42 ) ( 43 ) t i m e r y ( l o w ) p o r t p 5 d i r e c t i o n r e g i s t e r p o r t p 6 d i r e c t i o n r e g i s t e r p u l l r e g i s t e r b t i m e r y ( h i g h ) s e r i a l i / o 1 c o n t r o l r e g i s t e r u a r t c o n t r o l r e g i s t e r timer x (high) timer x (low) timer x mode register t i m e r y m o d e r e g i s t e r timer 123 mode register s e r i a l i / o 1 s t a t u s r e g i s t e r p o r t p 7 d i r e c t i o n r e g i s t e r a-d control register s e g m e n t o u t p u t e n a b l e r e g i s t e r l c d m o d e r e g i s t e r p u l l r e g i s t e r a i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r cpu mode register interrupt request register 1 interrupt request register 2 interrupt control register 1 i n t e r r u p t c o n t r o l r e g i s t e r 2 p r o c e s s o r s t a t u s r e g i s t e r p r o g r a m c o u n t e r p o r t p 4 d i r e c t i o n r e g i s t e r p o r t p 2 d i r e c t i o n r e g i s t e r p o r t p 3 o u t p u t c o n t r o l r e g i s t e r p o r t p 1 d i r e c t i o n r e g i s t e r p o r t p 0 d i r e c t i o n r e g i s t e r timer 1 timer 2 t i m e r 3 key input control register 111000 0 0 100000 0 0 001111 1 1 1 0 0 10 0 0 0 ? 1 ? ????? 00 16 00 16 00 16 00 16 00 16 00 16 ff 16 00 16 00 16 00 16 0 0 1 6 00 16 00 16 00 16 00 16 ff 16 ff 16 00 16 00 16 00 16 3 f 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ff 16 ff 16 contents of address fffd 16 c o n t e n t s o f a d d r e s s f f f c 1 6 d-a control register watchdog timer control register d - a 1 c o n v e r s i o n r e g i s t e r d-a2 conversion register serial i/o2 control register t o u t / o u t p u t c o n t r o l r e g i s t e r p w m c o n t r o l r e g i s t e r watchdog timer (high-order) ( 44 ) watchdog timer (low-order) ff 16 01 16 00 16 0 0 0 1 00 0 0 3 f 16 ff 16
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 48 clock generating circuit the 7560 group has two built-in oscillation circuits. an oscillation circuit can be formed by connecting a resonator between x in and x out (x cin and x cout ). use the circuit constants in accordance with the resonator manufacturer's recommended values. no exter- nal resistor is needed between x in and x out since a feed-back resistor exists on-chip. however, an external feed-back resistor is needed between x cin and x cout . to supply a clock signal externally, input it to the x in pin and make the x out pin open. the sub-clock x cin -x cout oscillation circuit cannot directly input clocks that are externally generated. accord- ingly, be sure to cause an external resonator to oscillate. immediately after poweron, only the x in oscillation circuit starts oscillating, and x cin and x cout pins go to high-impedance state. frequency control (1) middle-speed mode the internal clock is the frequency of x in divided by 8. after reset, this mode is selected. (2)high-speed mode the internal clock is half the frequency of x in . (3) low-speed mode the internal clock is half the frequency of x cin . a low-power consumption operation can be realized by stopping the main clock x in in this mode. to stop the main clock, set bit 5 of the cpu mode register to 1 . when the main clock x in is restarted, set enough time for oscil- lation to stabilize by programming. note: if you switch the mode between middle/high-speed and low- speed, stabilize both x in and x cin oscillations. the suffi- cient time is required for the sub-clock to stabilize, espe- cially immediately after power-on and at returning from stop mode. when switching the mode between middle/high- speed and low-speed, set the frequency in the condition that f(x in ) > 3 f(x cin ). fig. 52 ceramic resonator circuit fig. 53 external clock input circuit oscillation control (1) stop mode if the stp instruction is executed, the internal clock stops at an h level, and x in and x cin oscillators stop. timer 1 is set to ff 16 and timer 2 is set to 01 16 . either x in or x cin divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. the bits of the timer 123 mode register except bit 4 are cleared to 0 . set the timer 1 and timer 2 interrupt enable bits to disabled ( 0 ) before executing the stp instruction. oscillator restarts at reset or when an external interrupt is re- ceived, but the internal clock is not supplied to the cpu until timer 2 underflows. this allows time for the clock circuit oscillation to stabilize when a ceramic resonator is used. (2) wait mode if the wit instruction is executed, the internal clock stops at an h level. the states of x in and x cin are the same as the state be- fore the executing the wit instruction. the internal clock restarts at reset or when an interrupt is received. since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. x c i n c i n c o u t c c i n c c o u t r f r d x c o u t x i n x o u t x i n x o u t e x t e r n a l o s c i l l a t i o n c i r c u i t o p e n v cc v ss c c i n c c o u t r f r d x c i n x c o u t
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 49 fig. 54 clock generating circuit block diagram w i t i n s t r u c t i o n stp i nstruct i on ti m i ng (internal clock) s r q stp i nstruct i on s r q m a i n c l oc k stop bi t s r q t i m e r 2 ti mer 1 1 / 2 1/4 x i n x o u t x c o u t x cin i n t e r r u p t r e q u e s t r e s e t t i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t ti mer 2 count source selection bit l o w - s p e e d m o d e m i d d l e - / h i g h - s p e e d m o d e i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t ( n o t e ) middl e-spee d mo d e hi g h -spee d mo d e or low-speed mode n o t e : w h e n u s i n g t h e l o w - s p e e d m o d e , s e t t h e x c s w i t c h b i t t o 1 . m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t 0 1 1 0 1 0 i n t e r r u p t d i s a b l e f l a g i 1 / 2 1 0
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 50 fig. 55 state transitions of system clock n o t e s 1 : s w i t c h t h e m o d e b y t h e a r r o w s s h o w n b e t w e e n t h e m o d e b l o c k s . ( d o n o t s w i t c h b e t w e e n t h e m o d e d i r e c t l y w i t h o u t a n a r r o w . ) 2 : t h e a l l m o d e s c a n b e s w i t c h e d t o t h e s t o p m o d e o r t h e w a i t m o d e a n d r e t u r n e d t o t h e s o u r c e m o d e w h e n t h e s t o p m o d e o r t h e w a i t m o d e i s e n d e d . 3 : t i m e r a n d l c d o p e r a t e i n t h e w a i t m o d e . 4: w h e n t h e s t o p m o d e i s e n d e d , a d e l a y t i m e c a n b e s e t b y t i m e r 1 a n d t i m e r 2 i n m i d d l e - / h i g h - s p e e d m o d e . 5 : w h e n t h e s t o p m o d e i s e n d e d , a d e l a y t i m e i n l o w - s p e e d m o d e c a n b e s e t a s w e l l . 6 : w a i t u n t i l o s c i l l a t i o n s t a b i l i z e s a f t e r o s c i l l a t i n g t h e m a i n c l o c k x i n b e f o r e t h e s w i t c h i n g f r o m t h e l o w - s p e e d m o d e t o m i d d l e - / h i g h - s p e e d m o d e . 7 : t h e e x a m p l e a s s u m e s t h a t 8 m h z i s b e i n g a p p l i e d t o t h e x i n p i n a n d 3 2 k h z t o t h e x c i n p i n . i n d i c a t e s t h e i n t e r n a l c l o c k . cm 4 : x c sw i tc h bi t 0: oscillation stop 1: x cin , x cout cm 5 : main clock (x in ? out ) stop bit 0: oscillating 1: stopped cm 6 : main clock division ratio selection bit 0: f(x in )/2 (high-speed mode) 1: f(x in )/8 (middle-speed mode) cm 7 : internal system clock selection bit 0: x in ? out selected (middle-/high-speed mode) 1: x cin ? cout selected (low-speed mode ) cpu mo d e reg i ster (cpum : address 003b 16 ) b 7 b 4 r e s e t cm 7 = 0 ( 8 mh z se l ecte d) cm 6 = 1 (middle-speed) cm 5 = 0 (x in oscillating) m i d d l e - s p e e d m o d e ( = 1 m h z ) c m 7 = 0 ( 8 m h z s e l e c t e d ) c m 6 = 0 ( h i g h - s p e e d ) c m 5 = 0 ( x i n o s c i l l a t i n g ) hi g h -spee d mo d e ( = 4 mhz) c m 7 = 1 ( 3 2 k h z s e l e c t e d ) c m 6 = 1 ( m i d d l e - s p e e d ) c m 5 = 0 ( x i n o s c i l l a t i n g ) l ow-spee d mo d e ( =16 khz) cm 7 = 1 ( 32 kh z se l ecte d) cm 6 = 0 (high-speed) cm 5 = 0 (x in oscillating) l ow-spee d mo d e ( =16 khz) c m 7 = 1 ( 3 2 k h z s e l e c t e d ) c m 6 = 1 ( m i d d l e - s p e e d ) c m 5 = 1 ( x i n s t o p p e d ) l o w - s p e e d m o d e ( = 1 6 k h z ) cm 7 = 1 ( 32 kh z se l ecte d) cm 6 = 0 (high-speed) cm 5 = 1 (x in stopped) l o w - s p e e d m o d e ( = 1 6 k h z ) c m 6 ? ? cm 6 ? ? cm 6 0 1 c m 7 0 1 c m 7 0 1 c m 5 0 1 c m 5 0 1 c m 5 c m 6 0 1 0 1 c m 5 c m 6 0 1 1 0
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group 51 notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is 1 . af- ter a reset, initialize flags which affect program execution. in particular, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. interrupt the contents of the interrupt request bits do not change immedi- ately after they have been written. after writing to an interrupt re- quest register, execute at least one instruction before performing a bbc or bbs instruction. decimal calculations to calculate in decimal notation, set the decimal mode flag (d) to 1 , then execute an adc or sbc instruction. only the adc and sbc instructions yield proper decimal results. after executing an adc or sbc instruction, execute at least one instruction before executing a sec, clc, or cld instruction. in decimal mode, the values of the negative (n), overflow (v), and zero (z) flags are invalid. timers if a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n + 1). multiplication and division instructions the index mode (t) and the decimal mode (d) flags do not affect the mul and div instruction. the execution of these instructions does not change the contents of the processor status register. ports the contents of the port direction registers cannot be read. the following cannot be used: the data transfer instruction (lda, etc.) the operation instruction when the index x mode flag (t) is 1 the addressing mode which uses the value of a direction regis- ter as an index the bit-test instruction (bbc or bbs, etc.) to a direction register the read-modify-write instruction (ror, clb, or seb, etc.) to a direction register use instructions such as ldm and sta, etc., to set the port direc- tion registers. serial i/o in clock synchronous serial i/o, if the receive side is using an ex- ternal clock and it is to output the s rdy signal, set the transmit en- able bit, the receive enable bit, and the s rdy output enable bit to 1 . serial i/o1 continues to output the final bit from the t x d pin after transmission is completed. in serial i/o2, the s out2 pin goes to high impedance state after transmission is completed. a-d converter the comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. make sure that f(x in ) is at least 500khz during an a-d conversion. do not execute the stp or wit instruction during an a-d conver- sion. instruction execution time the instruction execution time is obtained by multiplying the fre- quency of the internal clock by the number of cycles needed to execute an instruction. the number of cycles required to execute an instruction is shown in the list of machine instructions. the frequency of the internal clock is half of the x in frequency. data required for mask orders the following are necessary when ordering a mask rom produc- tion: 1.mask rom order confirmation form ? 2.mark specification form ? 3.data to be written to rom, in eprom form (three identical cop- ies) or one floppy disk. ? for the mask rom confirmation and the mark specifications, re- fer to the mitsubishi mcu technical information homepage (http://www.infomicom.mesc.co.jp/indexe.htm).
52 single-chip 8-bit cmos microcomputer 7560 group mitsubishi microcomputers electrical characteristics absolute maximum ratings table 12 absolute maximum ratings recommended operating conditions table 13 recommended operating conditions (1) (v cc = 2.2 to 5.5 v, ta = ?0 to 85?, unless otherwise noted) power source voltage a-d, d-a conversion reference voltage analog power source voltage analog input voltage an 0 ?n 7 5.5 5.5 5.5 v cc v cc v cc v ss v ref av ss v ia symbol parameter limits min. v v v v v unit 4.0 2.2 2.2 2.0 av ss 5.0 5.0 5.0 0 0 typ. max. power source voltage v o v o v o pd topr tstg ?.3 to 6.5 v power source voltage input voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 input voltage p7 0 ?7 7 input voltage v l1 input voltage v l2 input voltage v l3 input voltage c 1 , c 2 input voltage reset, x in output voltage c 1 , c 2 v cc v i symbol parameter conditions ratings unit all voltages are based on v ss . output transistors are cut off. v i v i v i v i v i v i v o v o v o output voltage p0 0 ?0 7 , p1 0 ?1 5 , p3 0 ?3 7 output voltage p1 6 , p1 7 , p2 0 ?2 7 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 1 ?7 7 output voltage v l3 output voltage v l2 , seg 0 ?eg 17 output voltage x out power dissipation operating temperature storage temperature at output port at segment output ta = 25? ?.3 to v cc +0.3 ?.3 to v cc +0.3 ?.3 to v l2 v l1 to v l3 v l2 to 6.5 ?.3 to 6.5 ?.3 to v cc +0.3 ?.3 to 6.5 ?.3 to v cc ?.3 to v l3 ?.3 to v cc +0.3 ?.3 to 6.5 ?.3 to v l3 ?.3 to v cc +0.3 300 ?0 to 85 ?0 to 125 v v v v v v v v v v v v v v mw ? ? high-speed mode f(x in ) = 8 mhz middle-speed mode f(x in ) = 8 mhz low-speed mode
53 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group v v ??input voltage p0 0 ?0 7 , p1 0 ?1 7 , p4 0 , p4 3 , p4 5 , p4 7 , p5 0 ?5 3 , p5 6 , p6 1 , p6 4 ?6 7 , p7 1 ?7 7 ??input voltage p2 0 ?2 7 , p4 1 , p4 2 , p4 4 , p4 6 , p5 4 , p5 5 , p5 7 , p6 0 , p6 2 , p6 3 , p7 0 reset x in ??input voltage p0 0 ?0 7 , p1 0 ?1 7 , p4 0 , p4 3 , p4 5 , p4 7 , p5 0 ?5 3 , p5 6 , p6 1 , p6 4 ?6 7 , p7 1 ?7 7 ??input voltage p2 0 ?2 7 , p4 1 , p4 2 , p4 4 , p4 6 , p5 4 , p5 5 , p5 7 , p6 0 , p6 2 , p6 3 , p7 0 reset x in table 14 recommended operating conditions (2) (v cc = 2.5 to 5.5 v, ta = ?0 to 85?, unless otherwise noted) symbol parameter limits min. unit typ. max. ??input voltage ??input voltage v ih v ih v ih v ih v il v il v il v il ??input voltage ??input voltage 0.7 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0 0 0 0 v cc v cc v cc v cc 0.3 v cc 0.2 v cc 0.2 v cc 0.2 v cc v v v v v v v v ??input voltage p0 0 ?0 7 , p1 0 ?1 7 , p4 0 , p4 3 , p4 5 , p4 7 , p5 0 ?5 3 , p5 6 , p6 1 , p6 4 ?6 7 , p7 1 ?7 7 ??input voltage p2 0 ?2 7 , p4 1 , p4 2 , p4 4 , p4 6 , p5 4 , p5 5 , p5 7 , p6 0 , p6 2 , p6 3 , p7 0 reset x in ??input voltage p0 0 ?0 7 , p1 0 ?1 7 , p4 0 , p4 3 , p4 5 , p4 7 , p5 0 ?5 3 , p5 6 , p6 1 , p6 4 ?6 7 , p7 1 ?7 7 ??input voltage p2 0 ?2 7 , p4 1 , p4 2 , p4 4 , p4 6 , p5 4 , p5 5 , p5 7 , p6 0 , p6 2 , p6 3 , p7 0 reset x in table 15 recommended operating conditions (3) (v cc = 2.2 to 2.5 v, ta = ?0 to 85?, unless otherwise noted) symbol parameter limits min. unit typ. max. ??input voltage ??input voltage v ih v ih v ih v ih v il v il v il v il ??input voltage ??input voltage 0.8 v cc 0.95 v cc 0.95 v cc 0.95 v cc 0 0 0 0 v cc v cc v cc v cc 0.2 v cc 0.05 v cc 0.05 v cc 0.05 v cc v v v v v v
54 single-chip 8-bit cmos microcomputer 7560 group mitsubishi microcomputers p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 7 (note 1) p4 1 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 (note 1) p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 7 (note 1) p4 1 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 (note 1) p4 0 , p7 1 ?7 7 (note 1) p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 7 (note 1) p4 1 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 (note 1) p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 7 (note 1) p4 1 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 (note 1) p4 0 , p7 1 ?7 7 (note 1) p0 0 ?0 7 , p1 0 ?1 5 , p3 0 ?3 7 (note 2) ??peak output current p1 6 , p1 7 , p2 0 ?2 7 , p4 1 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 (note 2) p0 0 ?0 7 , p1 0 ?1 5 , p3 0 ?3 7 (note 2) ??peak output current p1 6 , p1 7 , p2 0 ?2 7 , p4 1 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 (note 2) p4 0 , p7 1 ?7 7 (note 2) p0 0 ?0 7 , p1 0 ?1 5 , p3 0 ?3 7 (note 3) p1 6 , p1 7 , p2 0 ?2 7 , p4 1 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 p0 0 ?0 7 , p1 0 ?1 5 , p3 0 ?3 7 (note 3) ??average output current p1 6 , p1 7 , p2 0 ?2 7 , p4 1 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 (note 3) p4 0 , p7 1 ?7 7 (note 3) ?0 ?0 20 20 80 ?0 ?0 10 10 40 ?.0 table 16 recommended operating conditions (4) (v cc = 2.2 to 5.5 v, ta = ?0 to 85?, unless otherwise noted) notes1: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an average value measured over 100 ms. the total peak current is the peak value of all the currents. 2: the peak output current is the peak current flowing in each port. 3: the average output current is an average value measured over 100 ms. ??total peak output current ??total peak output current ??total peak output current ??total peak output current ??total peak output current ??total average output current ??total average output current ??total average output current ??total average output current ??total average output current i oh(peak) i oh(peak) i ol(peak) i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) i ol(avg) i ol(avg) i oh(peak) symbol parameter limits min. ma ma ma ma ma ma ma ma ma ma ma unit typ. max. ??peak output current ??peak output current ??peak output current ??average output current ??average output current ??average output current ??average output current i oh(peak) i ol(peak) i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) i ol(avg) i ol(avg) ?.0 5.0 10 20 ?.5 ?.5 2.5 5.0 10 ma ma ma ma ma ma ma ma ma
55 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group table 17 recommended operating conditions (5) (v cc = 2.2 to 5.5 v, ta = ?0 to 85?, unless otherwise noted) notes1: when the oscillation frequency has a duty cycle of 50%. 2: when using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(x cin ) < f(x in )/3. input frequency for timers x and y (duty cycle 50%) f(cntr 0 ) f(cntr 1 ) symbol parameter limits min. mhz unit typ. max. (4.0 v v cc 5.5 v) 32.768 4.0 main clock input oscillation frequency (note 1) sub-clock input oscillation frequency (notes 1, 2) f(x in ) f(x cin ) (v cc 4.0 v) high-speed mode (4.0 v v cc 5.5 v) high-speed mode (2.2 v v cc 4.0 v) middle-speed mode (10 ? v cc ?)/9 8.0 (20 ? v cc ?)/9 8.0 50 mhz mhz mhz mhz khz test conditions
56 single-chip 8-bit cmos microcomputer 7560 group mitsubishi microcomputers v cc = 5.0 v, v o = v cc , pullup on output transistors ?ff v cc = 2.2 v,v o = v cc , pullup on output transistors ?ff i ol = 10 ma i ol = 3.0 ma i ol = 2.5 ma v cc = 2.2 v i ol = 5 ma i ol = 1.5 ma i ol = 1.25 ma v cc = 2.2 v v ol i oh = ? ma i oh = ?.25 ma v cc = 2.2 v i oh = ? ma i oh = ?.5 ma i oh = ?.25 ma v cc = 2.2 v v v cc ?.0 ??output voltage p0 0 ?0 7 , p1 0 ?1 5 , p3 0 ?3 7 symbol parameter limits min. unit 0.5 typ. max. test conditions v oh 2.0 0.5 table 18 electrical characteristics (1) (v cc =4.0 to 5.5 v, ta = ?0 to 85?, unless otherwise noted) i ol = 10 ma i ol = 5 ma v cc = 2.2 v v i = v cc v i = v cc v i = v cc v i = v ss pull-ups ?ff v cc = 5 v, v i = v ss pull-ups ?n v cc = 2.2 v, v i = v ss pull-ups ?n v i = v ss v i = v ss ??output voltage p1 6 , p1 7 , p2 0 ?2 7 , p4 1 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 (note 1) ??output voltage p0 0 ?0 7 , p1 0 ?1 5 , p3 0 ?3 7 ??output voltage p1 6 , p1 7 , p2 0 ?2 7 , p4 1 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 ??output voltage p4 0 , p7 1 ?7 7 hysteresis int 0 ?nt 2 , adt, cntr 0, cntr 1, p2 0 ?2 7 hysteresis s clk , r x d, s in2 hysteresis reset ??input current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 ??input current reset ??input current x in ??input current p0 0 ?0 7 ,p1 0 ?1 7 , p2 0 ?2 7 ,p4 1 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 ??input current p4 0 , p7 0 ?7 7 ??input current reset ??input current x in output load current p3 0 ?3 7 v oh v ol v ol v t+ ?v t v t+ ?v t v t+ ?v t i ih i ih i ih i il i il i il i load v cc ?.0 v cc ?.5 ?0.0 ?.0 0.5 0.5 4.0 ?20.0 ?0.0 ?.0 2.0 0.5 0.5 5.0 5.0 ?.0 ?40.0 ?0.0 ?.0 ?.0 ?40.0 ?0.0 v v v v v v v v v v a a a a a a a a i il v cc ?.8 v cc ?.8 v v v 0.8 v 0.8 0.3 v a a a v o = v cc , pullup off output transistors ?ff v o = v ss , pullup off output transistors ?ff output leak current p3 0 ?3 7 i leak 5.0 ?.0 a a ?20.0 ?0.0 ?0.0 ?.0
57 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group table 19 electrical characteristics (2) (v cc =2.2 to 5.5 v, ta = ?0 to 85?, unless otherwise noted) v 5.5 high-speed mode, v cc = 5 v f(x in ) = 8 mhz f(x cin ) = 32.768 khz output transistors ?ff a-d converter in operating high-speed mode, v cc = 5 v f(x in ) = 8 mhz (in wit state) f(x cin ) = 32.768 khz output transistors ?ff a-d converter stop low-speed mode, v cc = 5 v, ta 55? f(x in ) = stopped f(x cin ) = 32.768 khz output transistors ?ff low-speed mode, v cc = 5 v, ta = 25? f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors ?ff low-speed mode, v cc = 3 v, ta 55? f(x in ) = stopped f(x cin ) = 32.768 khz output transistors ?ff low-speed mode, v cc = 3 v, ta = 25? f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors ?ff all oscillation stopped (in stp state) output transistors ?ff symbol parameter limits min. unit typ. max. ta = 25 ? ta = 85 ? test conditions i cc power source current 8.0 v ram ram retention voltage at clock stop mode 2.0 when using voltage multiplier v l1 = 1.8 v v l1 i l1 power source voltage power source current (v l1 ) (note) note: when the voltage multiplier control bit of the lcd mode register (bit 4 at address 0039 16 ) is ?? 1.3 2.5 45 23 18 8 0.1 1.8 4.0 4.0 67 46 36 16 1.0 10 2.1 ma a a a a a v ma 15 a
58 single-chip 8-bit cmos microcomputer 7560 group mitsubishi microcomputers table 20 a-d converter characteristics (v cc = 2.7 to 5.5 v, v ss = av ss = 0 v, ta = ?0 to 85?, f(x in ) = 500 khz to 8 mhz, in middle/high-speed mode unless otherwise noted) symbol parameter limits min. unit typ. max. test conditions resolution absolute accuracy (excluding quantization error) v cc = v ref = 5 v bits lsb 35 150 8 ? 12.5 (note) 100 note: when an internal trigger is used in middle-speed mode, it is 14 s. s f(x in ) = 8 mhz conversion time ladder resistor reference power source input current t conv r ladder i vref k ? a table 21 d-a converter characteristics (v cc = 2.7 to 5.5 v, v cc = v ref , v ss = av ss = 0 v, ta = ?0 to 85?, in middle/high-speed mode unless otherwise noted) symbol parameter limits min. unit typ. max. test conditions resolution v cc = v ref = 5 v v cc = v ref = 2.7 v 1 bits % % s k ? ma 3 2.5 8 1.0 2.0 note: using one d-a converter, with the value in the d-a conversion register of the other d-a converter being ?0 16 ? and excluding currents flowing through the a-d resistance ladder. (note) setting time output resistor t su r o 4 3.2 12 50 absolute accuracy analog port input current i ia i vref reference power source input current a 200 5.0 v ref = 5 v
59 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group table 22 timing requirements 1 (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = ?0 to 85?, unless otherwise noted) 2 125 45 40 250 105 105 80 80 800 370 370 220 100 1000 400 400 200 200 note: when bit 6 of address 001a 16 is ?? divide this value by four when bit 6 of address 001a 16 is ?? reset input ??pulse width main clock input cycle time (x in input) main clock input ??pulse width main clock input ??pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input ??pulse width cntr 0 , cntr 1 input ??pulse width int 0 to int 2 input ??pulse width int 0 to int 2 input ??pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input ??pulse width (note) serial i/o1 clock input ??pulse width (note) serial i/o1 input set up time serial i/o1 input hold time serial i/o2 clock input cycle time (note) serial i/o2 clock input ??pulse width (note) serial i/o2 clock input ??pulse width (note) serial i/o2 input set up time serial i/o2 input hold time t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wl(cntr) t wh(int) t wl(int) t c(s clk1 ) t wh(s clk1 ) t wl(s clk1 ) t su(r x d? clk1 ) t h(s clk1 ? x d) t c(s clk2 ) t wh(s clk2 ) t wl (s clk2 ) t su(s in2 ? clk2 ) t h(s clk2 ? in2 ) symbol parameter limits min. s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns unit typ. max. table 23 timing requirements 2 (v cc = 2.2 to 4.0 v, v ss = 0 v, ta = ?0 to 85?, unless otherwise noted) 2 125 45 40 900/(v cc +0.4) t c(cntr) /2?0 t c(cntr) /2?0 230 230 2000 950 reset input ??pulse width main clock input cycle time (x in input) main clock input ??pulse width main clock input ??pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input ??pulse width cntr 0 , cntr 1 input ??pulse width int 0 to int 2 input ??pulse width int 0 to int 2 input ??pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input ??pulse width (note) t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wl(cntr) t wh(int) t wl(int) t c(s clk1 ) t wh(s clk1 ) symbol parameter limits min. s ns ns ns ns ns ns ns ns ns ns unit typ. max. note: when bit 6 of address 001a 16 is ?? divide this value by four when bit 6 of address 001a 16 is ?? t su(s in2 ? clk2 ) t h(s clk2 ? in2 ) t wl(s clk1 ) t su(r x d? clk1 ) t h(s clk1 ? x d) t c(s clk2 ) t wh(s clk2 ) t wl(s clk2 ) serial i/o1 clock input ??pulse width (note) serial i/o1 input set up time serial i/o1 input hold time serial i/o2 clock input cycle time (note) serial i/o2 clock input ??pulse width (note) serial i/o2 clock input ??pulse width (note) serial i/o2 input set up time serial i/o2 input hold time 950 400 200 2000 950 950 400 300 ns ns ns ns ns ns ns ns
60 single-chip 8-bit cmos microcomputer 7560 group mitsubishi microcomputers table 24 switching characteristics 1 (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = ?0 to 85?, unless otherwise noted) notes1: when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is ?? 2: x out and x cout pins are excluded. serial i/o1 clock output ??pulse width serial i/o1 clock output ??pulse width serial i/o1 output delay time (note 1) serial i/o1 output valid time (note 1) serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output ??pulse width serial i/o2 clock output ??pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) 140 30 30 0.2 ? t c (s clk2 ) 40 30 30 symbol parameter limits min. ns ns ns ns ns ns ns ns ns ns ns ns ns unit t c (s clk1 )/2?0 t c (s clk1 )/2?0 ?0 10 10 typ. max. t wh(s clk1 ) t wl(s clk1 ) t d(s clk1 ? x d) t v(s clk1 ? x d) t r(s clk1 ) t f(s clk1 ) t wh(s clk2 ) t wl(s clk2 ) t d(s clk2 ? out2 ) t v(s clk2 ? out2 ) t f(s clk2 ) t r(cmos) t f(cmos) table 25 switching characteristics 2 (v cc = 2.2 to 4.0 v, v ss = 0 v, ta = ?0 to 85?, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns ns ns ns unit notes1: when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is ?? 2: x out and x cout pins are excluded. serial i/o1 clock output ??pulse width serial i/o1 clock output ??pulse width serial i/o1 output delay time (note 1) serial i/o1 output valid time (note 1) serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output ??pulse width serial i/o2 clock output ??pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) 350 50 50 0.2 ? t c (s clk2 ) 50 50 50 symbol parameter limits min. t c (s clk1 )/2?0 t c (s clk1 )/2?0 ?0 20 20 max. t wh(s clk1 ) twl(s clk1 ) t d(s clk1 ? x d) t v(s clk1 ? x d) t r(s clk1 ) t f(s clk1 ) t wh(s clk2 ) t wl(s clk2 ) t d(s clk2 ? out2 ) t v(s clk2 ? out2 ) t f(s clk2 ) t r(cmos) t f(cmos) typ. t c (s clk2 )/2?60 t c (s clk2 )/2?60 0 t c (s clk2 )/2?40 t c (s clk2 )/2?40 0
61 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group fig. 56 circuit for measuring output switching characteristics m easurement output p i n 1 0 0 p f c m o s o u t p u t n o t e : w h e n p 7 1 p 7 7 , p 4 0 a n d b i t 4 o f t h e u a r t c o n t r o l r e g i s t e r ( a d d r e s s 0 0 1 b 1 6 ) i s 1 ( n - c h a n n e l o p e n - d r a i n o u t p u t m o d e ) . n - c h a n n e l o p e n - d r a i n o u t p u t ( n o t e ) 1 k ?
62 single-chip 8-bit cmos microcomputer 7560 group mitsubishi microcomputers fig. 57 timing diagram i n t 0 i n t 2 c n t r 0 , c n t r 1 0.2v cc t wl(int) 0 . 8 v c c t wh(int) 0 . 2 v c c 0.2v cc 0.8v cc 0 . 8 v c c 0.2v cc t wl(x in ) 0.8v cc t wh(x in) t c(x in ) x in 0 . 2 v c c 0 . 8 v c c t w ( r e s e t ) reset t f t r 0 . 2 v c c t wl(cntr) 0.8v cc t wh(cntr) t c(cntr) t d(s clk1 -t x d) ,t d(s clk2- s out2 ) t v(s clk1 -t x d), t v(s clk2- s out2 ) t c(s clk1 ), t c(s clk2 ) t wl(s clk1 ), t wl(s clk2 ) t wh(s clk1 ), t wh(s clk2 ) t h ( s c l k 1 - r x d ) , t h ( s c l k 2 - s i n 2 ) t su(r x d - s clk1 ), t su(s in2- s clk2 ) t x d s o u t 2 r x d s i n 2 s c l k 1 s c l k 2
63 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7560 group package outline lqfp100-p-1414-0.50 weight(g) e 0.63 jedec code eiaj package code lead material cu alloy 100p6q-a plastic 100pin 14 ? ?
?2001 mitsubishi electric corp. specifications subject to change without notice. notes regarding these materials these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product b est suited to the customer? application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party? rights, origina ting in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents inf ormation on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that c ustomers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assu mes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubish i semiconductor home page (http://www.mitsubishichips.com). when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used und er circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herei n for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these m aterials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licen se from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detai ls on these materials or the products contained therein. keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with a ppropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. head office: 2-2-3, marunouchi, chiyoda-ku, tokyo 100-8310, japan single-chip 8-bit cmos microcomputer 7560 group mitsubishi microcomputers
revision history 7560 group data sheet rev. date description page summary (1/1) 1.0 03/28/01 1.1 06/08/01 first edition table 13 v ref min. v cc +0.3 v cc 52

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